User manual

Section
7: TSP command reference Series 2600B System SourceMeter® Instrument
Reference Manual
7-284 2600BS-901-01 Rev. B / May 2013
status.operation.instrument.smuX.trigger_overrrun.*
This attribute contains the operation status SMU X trigger overrun register set.
Type TSP-Link accessible Affected by Where saved Default value
Attribute
- -
- -
- -
- -
.condition (R)
Yes
Not applicable
Not saved
Not applicable
.enable (RW)
Yes
Status reset
Not saved
0
.event (R) Yes Status reset Not saved 0
.ntr (RW)
Yes
Status reset
Not saved
0
.ptr (RW)
Yes
Status reset
Not saved
30 (All bits set)
Usage
operationRegister = status.operation.instrument.smuX.trigger_overrun.condition
operationRegister = status.operation.instrument.smuX.trigger_overrun.enable
operationRegister = status.operation.instrument.smuX.trigger_overrun.event
operationRegister = status.operation.instrument.smuX.trigger_overrun.ntr
operationRegister = status.operation.instrument.smuX.trigger_overrun.ptr
status.operation.instrument.smuX.trigger_overrun.enable = operationRegister
status.operation.instrument.smuX.trigger_overrun.ntr = operationRegister
status.operation.instrument.smuX.trigger_overrun.ptr = operationRegister
operationRegister
The status of the operation status SMU X trigger overrun register; a zero (0)
indicates no bits set (also send 0 to clear all bits); other values indicate various bit
settings
Details
These attributes are used to read or write to the operation status SMU X trigger overrun registers. Reading a
status register returns a value. The binary equivalent of the returned value indicates which register bits are set.
The least significant bit of the binary number is bit B0, and the most significant bit is bit B15. For example, if a
value of 18 is read as the value of the condition register, the binary equivalent is 0000 0000 0001 0010. This
value indicates that bit B1 and bit B4 are set.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
**
>
>
>
>
>
>
>
>
>
>
>
>
>
>
*
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
* Least significant bit
** Most significant bit
For information about .condition, .enable, .event, .ntr, and .ptr registers, refer to Status register set contents (on
page E-1) and Enable and transition registers (on page E-19). The individual bits of this register are defined in
the following table.