User manual
IEEE-488 Reference
4-70 2001-900-01 Rev. K / August 2010
The actual true state (high or low) of each Digital Output line depends on its programmed po-
larity. If programmed for active-high polarity, the output line will go high (true) when the upper
limit of LIMIT 1 is the first failure. If programmed for active-low polarity, the output line will
go low (true) when the upper limit of LIMIT 1 is the first failure. Polarity is programmed from
the Output subsystem (see paragraph 4.17).
Note that when the binning strobe is enabled (see :BSTRobe command path), output line #4 is
not considered to be part of the digital output pattern. The binning strobe uses line #4. With the
binning strobe enabled, parameters 8 through 15 are treated the same as parameters 0 through 7.
Programming example 10 OUTPUT 716; “:calc3:lim:upp:sour 4; sour?”
20 ENTER 716; A$
30 PRINT A$
40 END
Line 10 Specifies output line #3 to go true if the upper limit of LIMIT 1 is exceeded, and then
queries the source value.
Line 20 Addresses the Model 2001 to talk.
Line 30 Displays the source value (4).
:STATe <b>
:CALCulate3:LIMit[1]:STATe <b> Control LIMIT 1 test
:CALCulate3:LIMit2:STATe <b> Control LIMIT 2 test
Parameters <b> = 1 or ON Enable specified limit test
= 0 or OFF Disable specified limit test
Formats :calc3:lim:stat <b>
:calc3:lim2:stat <b>
Defaults Power-up Saved power-on setup
*RST OFF (both limit tests)
:SYSTem:PRESet OFF (both limit tests)
Query :STATe? Query state of specified limit test
Short-form formats: :calc3:lim:stat?
:calc3:lim2:stat?
Response message: 0 (off) or 1 (on)
Description These commands are used to enable or disable LIMIT 1 and LIMIT 2 tests. When enabled, the
test sequence for limits will be performed every time the instrument performs a measurement.
Testing is performed in the following sequence: Low Limit 1, High Limit 1, Low Limit 2 and
High Limit 2. Any limit test (LIMIT 1 or LIMIT 2) not enabled is simply not performed.
The first failure in the test sequence will determine which digital pattern will be applied to the
output port. For example, if the lower limit of LIMIT 1 fails, the digital pattern defined for LIM-
IT 1 lower limit failures will be applied to the output port. The other tests will still be performed,
but a failure will not change the digital pattern on the output port.