User manual
IEEE-488 Reference
2001-900-01 Rev. K/ August 2010 4-13
the Sequence Condition Register changes from 0 to 1. Con-
versely, when programmed for a negative transition, the bit
in the status register will set when the corresponding bit in
the condition register changes from 1 to 0.
The transition filter registers can be set or cleared by using
the following SCPI commands:
:STATus:OPERation:ARM:SEQuence:PT
Ransition <NRf>
:STATus:OPERation:ARM:SEQuence:NT
Ransition <NRf>
The transition filter registers can be read at any time by using
the following SCPI query commands:
:STATus:OPERation:ARM:SEQuence:PT
Ransition?
:STATus:OPERation:ARM:SEQuence:NT
Ransition?
Reading a transition filter register using the above query
commands does not affect the contents of the register.
The following operations will set (1) all the bits of the PTR
register and reset (0) all the bits of the NTR register:
1. Cycling power.
2. Sending the :STATus:PRESet command.
3. Sending the :STATus:OPERation:ARM:SE-
Quence:PTR 65535 and :STATus:OPERa-
tion:ARM:SEQuence:NTR 0 commands.
Sequence Event Register This is a latched, read-only
register whose bits are set by the Sequence Condition Regis-
ter and Transition Filter. Once a bit in this register is set, it
will remain set (latched) until the register is cleared by a spe-
cific clearing sequence. The bits of this register are logically
ANDed with the bits of the Sequence Event Enable Register
and applied to an OR gate. The output of the OR gate is ap-
plied to bit B1 of the Arm Condition Register (see paragraph
4.6.3). The following SCPI query command can be used to
read the Sequence Event Register:
:STATus:OPERation:ARM:SEQuence?
Reading this register using the above SCPI command clears
the register. The following list summarizes all operations
that will clear the Sequence Event Register:
1. Cycling power.
2. Sending the *CLS common command.
3. Sending the :STATus:OPERation:ARM:SEQuence?
query command.
Sequence Event Enable Register This register is pro-
grammed by the user and serves as a mask for the Sequence
Event Register. When masked, a set bit in the Sequence
Event Register will not set bit B1 of the Arm Condition Reg-
ister. Conversely, when unmasked, a set bit in the Sequence
Event Register will set the bit B1 of the Arm Condition Reg-
ister.
A bit in the Sequence Event Register is masked when the
corresponding bit in the Sequence Event Enable Register is
cleared (0). When the masked bit of the Sequence Event
Register sets, it is ANDed with the corresponding cleared bit
in the Sequence Event Enable Register. The logic “0” output
of the AND gate is applied to the input of the OR gate and
thus, will not set bit B1 of the Arm Condition Register.
A bit in the Sequence Event Register is unmasked when the
corresponding bit in the Sequence Event Enable Register is
set (1). When the unmasked bit of the Sequence Event Reg-
ister sets, it is ANDed with the corresponding set bit in the
Sequence Event Enable Register. The logic “1” output of the
AND gate is applied to the input of the OR gate and thus, will
set bit B1 of the Arm Condition Register.
The individual bits of the Sequence Event Enable Register
can be set or cleared by using the following SCPI command:
:STATus:OPERation:ARM:SEQuence:EN
ABle <NRf>
The following SCPI query command can be used to read the
Sequence Event Enable Register:
:STATus:OPERation:ARM:SEQuence:EN
ABle?
Reading this register using the above SCPI command will
not clear the register. The following list summarizes opera-
tions that will clear the Sequence Event Enable Register:
1. Cycling power.
2. Sending the
:STATus:OPERation:ARM:SEQuence:ENABle
0 command.
4.6.5 Trigger event status
The reporting of the trigger event is controlled by a set of 16-
bit registers; the Trigger Condition Register, the Transition
Filter, the Trigger Event Register, and the Trigger Event En-
able Register. cáÖìêÉ= QJNM= shows how these registers are
structured.
Bit B1 (Seq1) of the register set is used for the trigger event
(In trigger layer of Sequence 1). In general, Bit B1 sets when