User manual

IEEE-488 Reference
4-10 2001-900-01 Rev. K / August 2010
Event Register. When masked, a set bit in the Operation
Event Register will not set the Operation Summary Bit (OSB)
in the Status Byte Register. Conversely, when unmasked, a set
bit in the Operation Event Register will set the OSB bit.
A bit in the Operation Event Register is masked when the cor-
responding bit in the Operation Event Enable Register is
cleared (0). When the masked bit of the Operation Event Reg-
ister sets, it is ANDed with the corresponding cleared bit in
the Operation Event Enable Register. The logic “0” output of
the AND gate is applied to the input of the OR gate and thus,
will not set the OSB bit in the Status Byte Register.
A bit in the Operation Event Register is unmasked when the
corresponding bit in the Operation Event Enable Register is
set (1). When the unmasked bit of the Operation Event Reg-
ister sets, it is ANDed with the corresponding set bit in the
Operation Event Enable Register. The logic “1” output of the
AND gate is applied to the input of the OR gate and thus, will
set the OSB bit in the Status Byte Register.
The individual bits of the Operation Event Enable Register
can be set or cleared by using the following SCPI command:
:STATus:OPERation:ENABle <NRf>
The following SCPI query command can be used to read the
Operation Event Enable Register:
:STATus:OPERation:ENABle?
Reading this register using the above SCPI command does
not clear the register. The following list summarizes opera-
tions that will clear the Operation Event Enable Register:
1. Cycling power.
2. Sending the :STATus:PRESet command.
3. Sending the :STATus:OPERation:ENABle 0 command.
4.6.3 Arm event status
The reporting of the arm event is controlled by a set of 16-bit
registers; the Arm Condition Register, the Transition Filter,
the Arm Event Register, and the Arm Event Enable Register.
cáÖìêÉ=QJV= shows how these registers are structured. Notice
in cáÖìêÉ=QJR= that bit B1 (In An arm layer) of the Arm Con-
dition Register is controlled by the sequence event register set
(see paragraph 4.6.4 for details). In general, bit B1 sets when
the instrument is in the arm layer (arm layer 1) or scan layer
(armlayer 2) of operation. An explanation of the operation
process over bus is provided in paragraph 4.7.
The various registers used for arm event status are described
as follows. Note that these registers are controlled by the
:STATus:OPERation:ARM commands of the :STATus sub-
system (see paragraph 4.21).
 This is a real-time 16-bit read-
only register that constantly updates to reflect the ORed sum-
mary of the sequence event register set. In general, if bit B1
is set, the instrument is in an arm layer. The following SCPI
query command can be used to read the Arm Condition Reg-
ister:
:STATus:OPERation:ARM:CONDition?
The Arm Condition Register and the Transition Filter are
used to set the bits of the Arm Event Register. The Transition
Filter is discussed next.
 The transition filter is made up of
two 16-bit registers that are programmed by the user. It is
used to specify which transition (0 to 1, or 1 to 0) of bit B1 in
the Arm Condition Register will set bit B1 in the Arm Event
Register.
The filter can be programmed for positive transitions (PTR),
negative transitions (NTR) or both. When an event bit is pro-
grammed for a positive transition, the event bit in the Arm
Event Register will set when the corresponding bit in the Arm
Condition Register changes from 0 to 1. Conversely, when
programmed for a negative transition, the bit in the status reg-
ister will set when the corresponding bit in the condition reg-
ister changes from 1 to 0. The transition filter registers can be
set or cleared by using the following SCPI commands:
:STATus:OPERation:ARM:PTR <NRf>
:STATus:OPERation:ARM:NTR <NRf>
The transition filter registers can be read at any time by using
the following SCPI query commands:
:STATus:OPERation:ARM:PTR?
:STATus:OPERation:ARM:NTR?
Reading a transition filter register using the above query com-
mands does not affect the contents of the register.
The following operations will set (1) all the bits of the PTR
register and reset (0) all the bits of the NTR register:
1. Cycling power.
2. Sending the :STATus:PRESet command.
3. Sending the :STATus:OPERation:ARM:PTR 65535
and :STATus:OPERation:ARM:NTR 0 commands.