User manual

IEEE-488 Reference
2001-900-01 Rev. K/ August 2010 4-5
This indicator is on when the instrument is in the
talker active state. The unit is placed in this state by address-
ing it to talk with the correct MTA (My Talk Address) com-
mand. TALK is off when the unit is in the talker idle state.
The instrument is placed in the talker idle state by sending it
an UNT (Untalk) command, addressing it to listen, or with
the IFC (Interface Clear) command.
This indicator is on when the Model 2001 is in the
listener active state, which is activated by addressing the in-
strument to listen with the correct MLA (My Listen Address)
command. Listen is off when the unit is in the listener idle
state. The unit can be placed in the listener idle state by send-
ing UNL (Unlisten), addressing it to talk, or by sending IFC
(Interface Clear) over the bus.
The instrument can be programmed to generate a
service request (SRQ) when one or more errors or conditions
occur. When this indicator is on, a service request has been
generated. This indicator will stay on until the serial poll byte
is read or all the conditions which caused SRQ have ceased
to exist. See paragraph 4.6.8 for details.
4.5.3 LOCAL key
The LOCAL key cancels the remote state and restores local
operation of the instrument.
Pressing LOCAL also turns off the REM indicator and re-
turns the display to normal if a user defined message was dis-
played.
Note that the LOCAL key is also inoperative if the LLO (Lo-
cal Lockout) command is in effect.
4.6 Status structure
The status register structure of the Model 2001 is shown in
cáÖìêÉ=QJR=. The following information will explain the var-
ious registers and queues that make up this structure.
4.6.1 Standard event status
The reporting of standard events is controlled by two 16-bit
registers; the Standard Event Status Register and the Stan-
dard Event Status Enable Register. cáÖìêÉ=QJS= shows how
these registers are structured.
In general, the occurrence of a standard event sets the appro-
priate bit in the Standard Event Status Register. This register
can be read at any time to determine which, if any, standard
events have occurred. Also, with the proper use of the Stan-
dard Event Status Enable Register, a standard event can set
the Event Summary Bit (ESB) of the Status Byte Register.
This allows the programmer to take advantage of the service
request (SRQ) feature. See paragraph 4.6.9 for details.
 This is a latched, read
only register that is used to record the occurrence of standard
events. Each bit in the register (except bit B1 which is not
used by the Model 2001) represents a standard event.
Descriptions of these standard events are provided in
paragraph 4.10.4.
When a standard event occurs, the appropriate bit in the
Standard Event Status Register sets. For example, if you at-
tempt to read data from an empty Output Queue, a Query Er-
ror (QYE) will occur and set bit B2 of the status register. A
set bit in this register will remain set until an appropriate op-
eration is performed to clear the register. The Standard Event
Status Register can be read at any time by using the follow-
ing common query command (see paragraph 4.10.4 for de-
tails):
*ESR?
Reading this register using the *ESR? command also clears
the register. The following list summarizes all operations
that clear the Standard Event Status Register:
1. Cycling power.
2. Sending the *CLS common command.
3. Sending the *ESR? common command.
 This register is
programmed by the user and serves as a mask for standard
events. When a standard event is masked, the occurrence of
that event will not set the Event Summary Bit (ESB) in the
Status Byte Register. Conversely, when a standard event is
unmasked, the occurrence of that event will set the ESB bit.
A bit in the Standard Event Status Register is masked when
the corresponding bit in the Standard Event Status Enable
Register is cleared (0). When the masked bit of the Standard
Event Status Register sets, it is ANDed with the correspond-
ing cleared bit in the Standard Event Status Enable Register.
The logic “0” output of the AND gate is applied to the input
of the OR gate and thus, will not set the ESB bit in the Status
Byte Register.
A bit in the Standard Event Status Register is unmasked
when the corresponding bit in the Standard Event Status En-
able Register is set (1). When the unmasked bit of the Stan-
dard Event Status Register sets, it is ANDed with the
corresponding set bit in the Standard Event Status Enable
Register. The logic “1” output of the AND gate is applied to