User's Manual
Table Of Contents
- 1. Introduction
- The PN7150 architecture overview
- 2. NCI Overview
- 3. DH interface
- 5. Initialization & Operation configuration
- 6. Reader/Writer Mode
- 6.1 T1T, T2T, MIFARE Ultralight, MIFARE Classic and MIFARE Plus tags
- 6.1.1 Access through the [NCI] Frame RF Interface
- 6.1.2 [PN7150-NCI] extension: TAG-CMD Interface
- 6.1.3 [PN7150-NCI] extension: Payload structure of the TAG-CMD RF Interface
- 6.1.4 [PN7150-NCI] extension: REQs & RSPs rules
- 6.1.5 [PN7150-NCI] extension: List of REQs & RSPs
- 6.1.6 [PN7150-NCI] extension: raw data exchange REQs & RSPs
- 6.1.7 [PN7150-NCI] extension: T2T & MFU REQs & RSPs
- 6.1.8 [PN7150-NCI] extension: MIFARE Classic REQs & RSPs
- 6.1.9 Access through the TAG-CMD RF Interface
- 6.2 T3T tag
- 6.3 T4T & ISO-DEP Tags/Cards
- 6.3.1 Access through the Frame RF Interface
- 6.3.2 Access through the ISO-DEP RF Interface
- 6.3.3 [PN7150-NCI] extension: Presence check Command/Response
- 6.3.4 [PN7150-NCI] extension: S-Block Command/Response
- 6.3.5 [PN7150-NCI] extension: WTX notification
- 6.3.6 [PN7150-NCI] extension: Higher bit rates in Poll NFC-A & NFC-B
- 6.4 [PN7150-NCI] extension: 15693 & I-Code tags
- 6.5 [PN7150-NCI] extension: KOVIO tags
- 6.1 T1T, T2T, MIFARE Ultralight, MIFARE Classic and MIFARE Plus tags
- 7. Card Emulation Mode
- 8. P2P Initiator & Target Mode
- 9. RF Discovery Management
- 9.1 RF Discovery functionalities
- 9.2 NFC FORUM Profile as defined in [NCI]
- 9.3 [PN7150-NCI] extension: additional technologies not yet supported by the NFC FORUM
- 9.4 [PN7150-NCI] extension: Low Power Card Detector (LPCD) Mode
- 9.5 [PN7150-NCI] extension: EMVCo Profile in Poll & Listen Modes
- 9.6 [PN7150-NCI] extension: Power optimization
- 10. Configurations
- 11. Test Mode
- 12. PN7150 Practical approach
U
M10936
P
N7150 User Manual
UM
10936 All information provided in this document is subject to legal disclaimers.
U
ser manual
CO
MPANY PUBLIC
Rev. 2.0 — 6 November 2020
348120
86 of 127
Na
me & Rights
D
escription
Ex
t. Tag
L
en.
D
efault
Value
I
RQ_POLARITY_CFG
RW in E²PROM
Configuration of the IRQ pin polarity
Bit Mask Description
b7 b6 b5 b4 b3 b2 b1 b0
X I²C transport fragmentation
'1' => enabled,
'0'=> disabled
X I
RQ PIN polarity config.
0 0 0 0 0 0 A
ll these bits SHALL be set
to logical ‘0’ (RFU)
b1=
’0’ => PN7150 requests to transmit when IRQ pin = ’1’.
b1=’1’ => PN7150 requests to transmit when IRQ pin = ‘0’.
0xA0 0x05 1 0x00
VBAT
_MONITOR_EN_
CFG
RW in E²PROM
To Enable/Disable the Battery monitor & configure the
Threshold
Bit Mask Description
b7 b6 b5 b4 b3 b2 b1
b0
X V
bat Monitor Enable
X V
bat Monitor Threshold
0 0 0 0 0 0 RF
U
b0: ‘1’ to Enable, ‘0’ to disable.
b1: ‘1’ to set the threshold to 2.3V and ‘0’ to set it to 2.75V.
No
te: in NCI_RFST_DISCOVERY state, setting this parameter
w
ill be rejected by the NFCC with an INVALID PARAM status
‘0x09’ instead of SEMANTIC ERROR status ‘0x06’.
0
xA0 0x06 1 0x00
V
EN_CFG
RW in E²PROM
Configures the internal VEN signal, in case the VEN pin driver
is NOT supplied from PVDD. In such a case, when PVDD is
switched OFF, the VEN pin level in unknown, so the internal
VEN signal is defined by one bit in an internal register
(VEN_Value) while the VEN pin has to be pulled-down (to
avoid leakages) thanks to a 2
nd
bit in the same register
(VEN_Pulld) which has then to be set to '1' to activate the Pull
Down. These 2 bits can be configured through NCI thanks to
VEN_CFG LSbits, according to the following table:
Bit Mask Description
b7 b6 b5 b4 b3 b2 b1 b0
X VEN
_Value
X VEN
_Pulld
0 0 0 0 0 0 RFU
N
ote, in order to force a certain VEN value to be used
internally (no matter which state the external VEN pin level is
in) the VEN_Pulld value HAS to be set. Only if VEN_Pulld is
set and PVDD is switched off the internal VEN state will be
forced to what is specified in VEN_Value.
0xA0 0x07 1 0x03