User's Manual
Table Of Contents
- 1. Introduction
- The PN7150 architecture overview
- 2. NCI Overview
- 3. DH interface
- 5. Initialization & Operation configuration
- 6. Reader/Writer Mode
- 6.1 T1T, T2T, MIFARE Ultralight, MIFARE Classic and MIFARE Plus tags
- 6.1.1 Access through the [NCI] Frame RF Interface
- 6.1.2 [PN7150-NCI] extension: TAG-CMD Interface
- 6.1.3 [PN7150-NCI] extension: Payload structure of the TAG-CMD RF Interface
- 6.1.4 [PN7150-NCI] extension: REQs & RSPs rules
- 6.1.5 [PN7150-NCI] extension: List of REQs & RSPs
- 6.1.6 [PN7150-NCI] extension: raw data exchange REQs & RSPs
- 6.1.7 [PN7150-NCI] extension: T2T & MFU REQs & RSPs
- 6.1.8 [PN7150-NCI] extension: MIFARE Classic REQs & RSPs
- 6.1.9 Access through the TAG-CMD RF Interface
- 6.2 T3T tag
- 6.3 T4T & ISO-DEP Tags/Cards
- 6.3.1 Access through the Frame RF Interface
- 6.3.2 Access through the ISO-DEP RF Interface
- 6.3.3 [PN7150-NCI] extension: Presence check Command/Response
- 6.3.4 [PN7150-NCI] extension: S-Block Command/Response
- 6.3.5 [PN7150-NCI] extension: WTX notification
- 6.3.6 [PN7150-NCI] extension: Higher bit rates in Poll NFC-A & NFC-B
- 6.4 [PN7150-NCI] extension: 15693 & I-Code tags
- 6.5 [PN7150-NCI] extension: KOVIO tags
- 6.1 T1T, T2T, MIFARE Ultralight, MIFARE Classic and MIFARE Plus tags
- 7. Card Emulation Mode
- 8. P2P Initiator & Target Mode
- 9. RF Discovery Management
- 9.1 RF Discovery functionalities
- 9.2 NFC FORUM Profile as defined in [NCI]
- 9.3 [PN7150-NCI] extension: additional technologies not yet supported by the NFC FORUM
- 9.4 [PN7150-NCI] extension: Low Power Card Detector (LPCD) Mode
- 9.5 [PN7150-NCI] extension: EMVCo Profile in Poll & Listen Modes
- 9.6 [PN7150-NCI] extension: Power optimization
- 10. Configurations
- 11. Test Mode
- 12. PN7150 Practical approach
U
M10936
P
N7150 User Manual
UM
10936 All information provided in this document is subject to legal disclaimers.
U
ser manual
CO
MPANY PUBLIC
Rev. 2.0 — 6 November 2020
348120
85 of 127
Na
me & Rights
D
escription
Ex
t. Tag
L
en.
D
efault
Value
C
LOCK_SEL_CFG
RW in E²PROM
Input Clock selection & configuration for the internal 13.56MHz
CLOCK
Bits [4:3] Clk Source Description
01b XT
AL A 27.12MHz quartz has to be
connected to PN7150
10b PL
L
A clean clock signal has to be
directly provided on the Clock
pad (bits [2:0] have to be
configured in addition to specify
the clock value, see the table
below)
11b RF
U
00b RF
U
W
hen the PLL is used, the bits [2:0] have to be configured
according to the following table, depending on the clock
provided to PN7150
Bits [2:0] Clk In
000b 13.
0 MHz
001b 19.
2 MHz
010b 24 MHz
011b 26.
0 MHz
100b 38.
4 MHz
101b 52 MHz
110b-1
11b RFU
0
xA0 0x03 1 0x08
CL
OCK_TO_CFG
RW in E²PROM
Indicates the timeout value to be used for clock request
acknowledgment (from 1.53ms to 10 ms in steps of 330µs).
So the actual Time Out value (in µs) is given by the following
formula:TimeOut (µs) = 1200 + (CLOCK_TO_CFG)*330
Minimum value is 01. Value 0x00 SHALL NOT be used,
otherwise there is no timeout (no wait time). In this case
the PLL is started immediately without waiting for the external
sys_clock.
Maximum value to be used is 0x06, to ensure the NFCC is
ready to reply 5ms after an external field on.
0xA0 0x04 1 0x01