User's Manual
Table Of Contents
- 1. Introduction
- The PN7150 architecture overview
- 2. NCI Overview
- 3. DH interface
- 5. Initialization & Operation configuration
- 6. Reader/Writer Mode
- 6.1 T1T, T2T, MIFARE Ultralight, MIFARE Classic and MIFARE Plus tags
- 6.1.1 Access through the [NCI] Frame RF Interface
- 6.1.2 [PN7150-NCI] extension: TAG-CMD Interface
- 6.1.3 [PN7150-NCI] extension: Payload structure of the TAG-CMD RF Interface
- 6.1.4 [PN7150-NCI] extension: REQs & RSPs rules
- 6.1.5 [PN7150-NCI] extension: List of REQs & RSPs
- 6.1.6 [PN7150-NCI] extension: raw data exchange REQs & RSPs
- 6.1.7 [PN7150-NCI] extension: T2T & MFU REQs & RSPs
- 6.1.8 [PN7150-NCI] extension: MIFARE Classic REQs & RSPs
- 6.1.9 Access through the TAG-CMD RF Interface
- 6.2 T3T tag
- 6.3 T4T & ISO-DEP Tags/Cards
- 6.3.1 Access through the Frame RF Interface
- 6.3.2 Access through the ISO-DEP RF Interface
- 6.3.3 [PN7150-NCI] extension: Presence check Command/Response
- 6.3.4 [PN7150-NCI] extension: S-Block Command/Response
- 6.3.5 [PN7150-NCI] extension: WTX notification
- 6.3.6 [PN7150-NCI] extension: Higher bit rates in Poll NFC-A & NFC-B
- 6.4 [PN7150-NCI] extension: 15693 & I-Code tags
- 6.5 [PN7150-NCI] extension: KOVIO tags
- 6.1 T1T, T2T, MIFARE Ultralight, MIFARE Classic and MIFARE Plus tags
- 7. Card Emulation Mode
- 8. P2P Initiator & Target Mode
- 9. RF Discovery Management
- 9.1 RF Discovery functionalities
- 9.2 NFC FORUM Profile as defined in [NCI]
- 9.3 [PN7150-NCI] extension: additional technologies not yet supported by the NFC FORUM
- 9.4 [PN7150-NCI] extension: Low Power Card Detector (LPCD) Mode
- 9.5 [PN7150-NCI] extension: EMVCo Profile in Poll & Listen Modes
- 9.6 [PN7150-NCI] extension: Power optimization
- 10. Configurations
- 11. Test Mode
- 12. PN7150 Practical approach
U
M10936
P
N7150 User Manual
UM
10936 All information provided in this document is subject to legal disclaimers.
U
ser manual
CO
MPANY PUBLIC
Rev. 2.0 — 6 November 2020
348120
84 of 127
1
0. Configurations
!
W
hen the DH needs to update the value of the parameters described
hereafter, it shall send a CORE_RESET_CMD/CORE_INIT_CMD sequence
after the CORE_SET_CONFIG_CMD, to ensure that the new value is used
for the parameters.
If numerous parameters are updated thanks to multiple
CORE_SET_CONFIG_CMD commands, a single CORE_RESET_CMD/
CORE_INIT_CMD sequence is enough after the last
CORE_SET_CONFIG_CMD.
!
An
y CORE_SET_CONFIG_CMD to one of the following parameters or to the
[NCI] standard parameters will trigger an EEPROM write cycle. Since the
PN7150 EEPROM has a limited number of Erase/Write cycles (300 000), it is
highly recommended to only use the CORE_SET_CONFIG_CMD during the
NCI initialization sequence.
10.1 [PN7150-NCI] extension: System configurations
P
N7150 offers several parameters used to configure the system aspects.
Table 82. Core configuration parameters
Na
me & Rights
D
escription
Ex
t. Tag
L
en.
D
efault
Value
CL
OCK_REQUEST_CFG
RW in E²PROM
Indicates how the clock is requested to the DH by the
PN7150.
0x00 Clock Request is disabled
0x
01 Hardware-based Clock Request is enabled:
CLKREQ pin set to high when clock
requested, otherwise it is set to hi-Z (High
Impedance).
0x
02-0xFF RFU
0
xA0 0x02 1 0x01