User's Manual

U
M10936
P
N7150 User Manual
UM
10936 All information provided in this document is subject to legal disclaimers.
U
ser manual
CO
MPANY PUBLIC
Rev. 2.0 — 6 November 2020
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44 of 127
5.6 PLL input Clock Management
T
he PN7150 is flexible in terms of clock sources. It can be either:
 a 27.12MHz quartz
 or a clean clock signal available on the platform on which PN7150 is connected.
A PLL inside PN7150 will convert this input clock signal into an internal 27.12MHz
used to generate the RF carrier. The input clock frequency has to be one of the
predefined set of input frequencies: 13MHz, 19.2MHz, 24MHz, 26MHz, 38.4MHz
and 52MHz.
The DH has to configure the parameter CLOCK_SEL_CFG (see chapter →10.1) to
configure what is the clock source as used in the current application.
T
able 26. Clock sources supported
Name Description
XT
AL To be selected when a 27.12MHz quartz is used as a clock source
PLL
T
o be selected when an input clock is provided to PN7150, with a frequency
equal to either 13MHz, 19.2MHz, 24MHz, 26MHz, 38.4MHz or 52MHz
T
he same parameter (CLOCK_SEL_CFG) is used to configure which clock frequency is
used as an input to the PLL when this is the clock source in use.
In order to optimize system power consumption, it may be required to switch OFF the PLL
input clock when the PN7150 does not have to generate the 13.56MHz RF carrier.
A dedicated pin (CLKREQ) is used to inform the DH or a clock generating chip that the
PN7150 requires to get the PLL input clock, such that it can generate the 13.56MHz RF
carrier. PN7150 assumes that the PLL input clock is on and stable after a programmable
time-out, which is configured thanks to the parameter CLOCK_TO_CFG (see chapter
→10.1).
5.7 Transmitter voltage Configurations
T
he PN7150 supports 2 different configurations, called CFG1 and CFG2.