User's Manual

U
M10936
P
N7150 User Manual
UM
10936 All information provided in this document is subject to legal disclaimers.
U
ser manual
CO
MPANY PUBLIC
Rev. 2.0 — 6 November 2020
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20 of 127
I
t may send an I²C NACK (negative acknowledge) when none of the buffers used by the
NCI core in the PN7150 is free, which may happen in case PN7150 is in standby mode. If
one single byte of a complete NCI frame is NACKed by the PN7150, the DH has to re-
send the complete NCI frame and not only this single byte.
SCL
NCI Header
Byte 0
NCI Header
Byte 1
NCI Payload
Length
NCI Payload
Byte 0
NCI Payload
Byte n-2
NCI Payload
Byte n-1
NCI Payload
Byte n
I²C Slave Address
+ R/W bit = 0b
SDA
IRQ
I²C Start
I²C Stop
F
ig 14. I²C Write sequence
!
It may happen that PN7150 has an NCI Message ready to be sent to the DH while
it is receiving another NCI Message from the DH. In such a condition, the IRQ pin
will be raised somewhere during the Write Sequence: this is not an error and has
to be accepted by the DH: once the Write Sequence is completed, the DH has to
start a Read Sequence (see →3.4).
3
.4 Read Sequence from the DH
The
DH shall never initiate a spontaneous I²C read request. The DH shall wait until it is
triggered by the PN7150.
To trigger the DH, the PN7150 generates a logical transition from Low to High on its IRQ
pin (if the IRQ pin is configured to be active High; see configuration chapter →10.1). So
after writing any NCI command, the DH shall wait until the PN7150 raises its IRQ pin.
The DH can then transmit a Read request to fetch the NCI answer from the PN7150. When
the PN7150 needs to send a spontaneous notification to the DH (for instance an RF
Interface activation notification), the PN7150 raises the IRQ pin and the DH performs a
normal read as described above.
A DH Read Sequence always starts by the sending of the PN7150 I²C Slave Address
followed by the read bit (logical ‘1’). Then the DH I²C interface sends an ACK back to the
PN7150 for each data Byte received.
Fig 15 is an example where the IRQ is raised so the DH can proceed a read.
DH knows how often
to Apply the clock
SCL
If the DH sends more
clocks, zeros will be sent
NCI Header
Byte 0
NCI Header
Byte 1
NCI Payload
Length
NCI Payload
Byte 0
NCI Payload
Byte n-2
NCI Payload
Byte n-1
NCI Payload
Byte n
I²C Slave Address
+ R/W bit = 1b
SDA
IRQ
NFCC requests
a transfer
All data has been
read, IRQ is reset
If NFCC requests a transfer, but DH sets
R/W bit to 0b, IRQ will remain high.
I²C Start
I²C Stop
F
ig 15. I²C Read sequence