User's Manual
Table Of Contents
- 1. Introduction
- The PN7150 architecture overview
- 2. NCI Overview
- 3. DH interface
- 5. Initialization & Operation configuration
- 6. Reader/Writer Mode
- 6.1 T1T, T2T, MIFARE Ultralight, MIFARE Classic and MIFARE Plus tags
- 6.1.1 Access through the [NCI] Frame RF Interface
- 6.1.2 [PN7150-NCI] extension: TAG-CMD Interface
- 6.1.3 [PN7150-NCI] extension: Payload structure of the TAG-CMD RF Interface
- 6.1.4 [PN7150-NCI] extension: REQs & RSPs rules
- 6.1.5 [PN7150-NCI] extension: List of REQs & RSPs
- 6.1.6 [PN7150-NCI] extension: raw data exchange REQs & RSPs
- 6.1.7 [PN7150-NCI] extension: T2T & MFU REQs & RSPs
- 6.1.8 [PN7150-NCI] extension: MIFARE Classic REQs & RSPs
- 6.1.9 Access through the TAG-CMD RF Interface
- 6.2 T3T tag
- 6.3 T4T & ISO-DEP Tags/Cards
- 6.3.1 Access through the Frame RF Interface
- 6.3.2 Access through the ISO-DEP RF Interface
- 6.3.3 [PN7150-NCI] extension: Presence check Command/Response
- 6.3.4 [PN7150-NCI] extension: S-Block Command/Response
- 6.3.5 [PN7150-NCI] extension: WTX notification
- 6.3.6 [PN7150-NCI] extension: Higher bit rates in Poll NFC-A & NFC-B
- 6.4 [PN7150-NCI] extension: 15693 & I-Code tags
- 6.5 [PN7150-NCI] extension: KOVIO tags
- 6.1 T1T, T2T, MIFARE Ultralight, MIFARE Classic and MIFARE Plus tags
- 7. Card Emulation Mode
- 8. P2P Initiator & Target Mode
- 9. RF Discovery Management
- 9.1 RF Discovery functionalities
- 9.2 NFC FORUM Profile as defined in [NCI]
- 9.3 [PN7150-NCI] extension: additional technologies not yet supported by the NFC FORUM
- 9.4 [PN7150-NCI] extension: Low Power Card Detector (LPCD) Mode
- 9.5 [PN7150-NCI] extension: EMVCo Profile in Poll & Listen Modes
- 9.6 [PN7150-NCI] extension: Power optimization
- 10. Configurations
- 11. Test Mode
- 12. PN7150 Practical approach
U
M10936
P
N7150 User Manual
UM
10936 All information provided in this document is subject to legal disclaimers.
U
ser manual
CO
MPANY PUBLIC
Rev. 2.0 — 6 November 2020
348120
19 of 127
3
. DH interface
3.1 Introduction
T
he I²C interface of the PN7150 is compliant with the I²C Bus Specification V3.0, including
device ID and Soft Reset. It is slave-only, i.e. the SCL signal is an input driven by the host.
!
N
CI packets can be as long as 258 Bytes. If the DH I²C peripheral has a buffer
limitation which is below 258 Bytes, then a fragmentation mechanism SHALL be
used at the I²C transport layer, as defined in →3.6.
T
he PN7150 I²C interface supports standard (up to 100kbps), fast-Speed mode (up to
400kbps) and High Speed mode (up to 3.4Mbit/s).
I
²C defines two different modes of addressing (7-bit & 10-bit). The PN7150 only supports
t
he 7-bit addressing mode.
T
he PN7150 I²C 7-bit address can be configured from 0x28 to 0x2B. The 2 least significant
bits of the slave address are electrically forced by pins I2C_ADR0 and I2C_ADDR1 of the
PN7150.
So, in binary format, the PN7150 slave 7-bit address is:
“0 1 0 1 0 I2C_ADDR1 I2C_ADDR0”
T
able 3. PN7150 I²C slave address
A
ddress Value
I
2C_ADDR1 Pin
I
2C_ADDR0 Pin
0x
28 0 0
0x29 0 1
0x
2A 1 0
0x
2B 1 1
T
his can be easily configured through direct connection of pins I2C_ADDR0 and
I2C_ADDR1 to either GND or PVDD at PCB level.
3
.2 NCI Transport Mapping
I
n the PN7150, there is no additional framing added for I²C: an NCI packet (either data or
control message, as defined in chapter →2.3) is transmitted over I²C “as is”, i.e. without
any additional Byte (no header, no CRC etc…).
3.3 Write Sequence from the DH
A
s the I²C clock is mastered by the DH, only the DH can initiate an I²C exchange.
A DH write sequence always starts with the sending of the PN7150 I²C Slave Address
followed by the write bit (logical ‘0’: 0b). Then the PN7150 I²C interface sends an I²C ACK
back to the DH for each data byte written by the DH.