Projector Service Manual
Table Of Contents
- DECLARATION OF CONFORMITY
- BZSAFE.PDF
- CH1INTRO.PDF
- CH2SYSDE.PDF
- Functional Descriptions
- Contents
- Cover and Base
- External Power Requirements
- Electronics Systems Overview
- System Power
- Card Cage
- Circuit Boards
- Raster Timing Generator Board (RTG) p/n 100568
- Sync Generator
- Sync Detector and Selector
- Serration and Equalization Lockout
- Phase Locked Loop
- VSYNC Detector, Field Separator, and Mux
- Adjustment Counters
- Serial Communication
- Raster Timing Generator I/O
- Interlocks and Protection
- Horizontal Deflection Board P/N 102523 (HDB)
- Vertical Oscillator
- Horizontal Phase Locked Loop
- Horizontal Centering
- Horizontal Power Supply
- Flyback Switching
- Geometric Correction
- Output Section
- Horizontal Sweep Failure Detection
- Serial Communication
- Horizontal Deflection Board I/O
- Interlocks and Protection
- Vertical Deflection Board P/N 102521(VDB)
- Vertical Preamps
- Vertical Amplifiers
- Sweep Failure Detection
- Side Pincushion and Keystone Correction
- Horizontal Linearity Correction
- Top and Bottom Pincushion and Keystone Correction
- Correction Amplifiers
- Serial Communication
- General I/O
- Interlocks and Shutdowns
- Video Processor Board P/N 104672 (VPB)
- Decoder
- Video/Sync Mux
- V & H Sync Strip
- SG Sync Strip
- B, G, and R Brightness and Contrast Amplifiers
- On-Screen Switch
- Gamma Correction
- Switch Logic and Video Enable
- RGB Sensitivity and Threshold Amplifier
- ILA® Bias
- Dynamic Focus Amplifier
- Serial Communication
- General I/O
- Interlocks and Protection
- Video Amplifier Board P/N 103567 or 103774 (VAB)
- Video Signal
- Failure Detection
- Beam Current Sense
- DC Restore
- Arc Protection
- Blanking
- Enable Circuit
- Focus
- Filament Supply
- General I/O
- System Controller Board P/N 104668 (SCB)
- General Functional Description
- CPU
- Working and Compressed Memory
- Expanded Memory
- Correction Address Generator
- DACs
- DSP
- Overlay Memory
- Overlay Address Generator
- Overlay Interface
- LED Display Buffers and Logic
- RS232 Interface
- IR Interface
- IIC Interface
- Serial Interface
- General I/O
- Backplane Board p/n 100571
- Optical Section
- Image Light Amplifier
- Functional Descriptions
- CH3ADJST.PDF
- CH4MAINT.PDF
- Maintenance Remove/Replace)
- Contents
- Introduction
- Projector Covers
- Ventilation Filters
- Arc Lamp Assembly
- System Power Supply
- Electronics Module
- Cathode Ray Tube (CRT)
- Video Amplifier Board (VAB)
- CRT Yoke
- High Voltage Power Supply (HVPS)
- Card Cage (Printed Circuit Boards)
- Image Light Amplifier Assembly
- Projection Lens
- (SCB) Socket Battery Replacement
- Recommended Spares
- Maintenance Remove/Replace)
- CH5TRBSH.PDF
- HGLOSS.PDF

Chapter 2—Functional Description
Model 330, 340SC and 370SC Service Manual 2-63
The digital information that is to be used for raster correction is stored in bit-map
form. The bit-map is 96 fields (out of 112) wide by the number of horizontal lines
in a frame wide. Each address in the EXM corresponds to a small section of one
(1) line on the screen.
As the raster is scanned, the EXM is being read out so that during the time that
each line of the raster is being scanned, 96 memory locations are being read. In
this way, each area of the raster can be accurately corrected.
Since there are twelve (12) functions to be corrected (R, G, and B for each of X
registration, Y registration, Threshold, and Sensitivity), each memory corresponds
to one correction function. All twelve (12) memories are read out simultaneously,
one (1) address at a time, to provide the correction required for the raster.
Correction Address Generator
The Correction Address Generator is used to address the EXM during both load
and readout. During the loading time, when the DSP is writing to the EXM, the
DSP controls the address generator, both setup and timing. During the time when
writing is not occurring, the memory is being read. At that time, the address
generator is set up by the DSP, but it’s timing signals come from the RTG to
synchronize it with raster generation.
During the read times, the address generator uses the /CORRSTRT and /MAPST
signals from the RTG as timing signals. The timing clock used is the /HX112
signal. Thus, the address generator generates addresses at the rate of 112 times the
horizontal frequency. It does this for 96 clock pulses, then stops. After the next
/CORRSTRT signal, it generates another 96 addresses. This repeats for each line
in the raster. The starting address is timed by the /MAPST signal. When that
comes along, it indicates the top of the raster is beginning so the address generator
should begin counting at the beginning.
During writing times, as the DSP generates data, it causes the address generator to
increment to the proper address to be loaded.
DACs
The Digital to Analog Converters are used to convert the digital data stored in the
EXMs to analog form for use by the correction amplifiers. There are twelve (12)
DACs, one (1) for each memory. Six (6) of the DACs are for X-Y registration and
send their outputs to the VDB. The other six (6) DACs are for shading (Threshold
and Sensitivity) and send their outputs to the VPB. The data from the DACs is
real time data that corrects the raster as it is scanned.
DSP
The Digital Signal Processor is a slave processor that operates under the control of
the CPU. The DSP does the processing that converts the raw convergence and
shading numbers that the operator inputs, into the smooth correction data that










