Projector Service Manual
Table Of Contents
- DECLARATION OF CONFORMITY
- BZSAFE.PDF
- CH1INTRO.PDF
- CH2SYSDE.PDF
- Functional Descriptions
- Contents
- Cover and Base
- External Power Requirements
- Electronics Systems Overview
- System Power
- Card Cage
- Circuit Boards
- Raster Timing Generator Board (RTG) p/n 100568
- Sync Generator
- Sync Detector and Selector
- Serration and Equalization Lockout
- Phase Locked Loop
- VSYNC Detector, Field Separator, and Mux
- Adjustment Counters
- Serial Communication
- Raster Timing Generator I/O
- Interlocks and Protection
- Horizontal Deflection Board P/N 102523 (HDB)
- Vertical Oscillator
- Horizontal Phase Locked Loop
- Horizontal Centering
- Horizontal Power Supply
- Flyback Switching
- Geometric Correction
- Output Section
- Horizontal Sweep Failure Detection
- Serial Communication
- Horizontal Deflection Board I/O
- Interlocks and Protection
- Vertical Deflection Board P/N 102521(VDB)
- Vertical Preamps
- Vertical Amplifiers
- Sweep Failure Detection
- Side Pincushion and Keystone Correction
- Horizontal Linearity Correction
- Top and Bottom Pincushion and Keystone Correction
- Correction Amplifiers
- Serial Communication
- General I/O
- Interlocks and Shutdowns
- Video Processor Board P/N 104672 (VPB)
- Decoder
- Video/Sync Mux
- V & H Sync Strip
- SG Sync Strip
- B, G, and R Brightness and Contrast Amplifiers
- On-Screen Switch
- Gamma Correction
- Switch Logic and Video Enable
- RGB Sensitivity and Threshold Amplifier
- ILA® Bias
- Dynamic Focus Amplifier
- Serial Communication
- General I/O
- Interlocks and Protection
- Video Amplifier Board P/N 103567 or 103774 (VAB)
- Video Signal
- Failure Detection
- Beam Current Sense
- DC Restore
- Arc Protection
- Blanking
- Enable Circuit
- Focus
- Filament Supply
- General I/O
- System Controller Board P/N 104668 (SCB)
- General Functional Description
- CPU
- Working and Compressed Memory
- Expanded Memory
- Correction Address Generator
- DACs
- DSP
- Overlay Memory
- Overlay Address Generator
- Overlay Interface
- LED Display Buffers and Logic
- RS232 Interface
- IR Interface
- IIC Interface
- Serial Interface
- General I/O
- Backplane Board p/n 100571
- Optical Section
- Image Light Amplifier
- Functional Descriptions
- CH3ADJST.PDF
- CH4MAINT.PDF
- Maintenance Remove/Replace)
- Contents
- Introduction
- Projector Covers
- Ventilation Filters
- Arc Lamp Assembly
- System Power Supply
- Electronics Module
- Cathode Ray Tube (CRT)
- Video Amplifier Board (VAB)
- CRT Yoke
- High Voltage Power Supply (HVPS)
- Card Cage (Printed Circuit Boards)
- Image Light Amplifier Assembly
- Projection Lens
- (SCB) Socket Battery Replacement
- Recommended Spares
- Maintenance Remove/Replace)
- CH5TRBSH.PDF
- HGLOSS.PDF
Chapter 2—Functional Descriptions
2-24 Model 330. 340SC, and 370SC Service Manual
/Hx112
112 times the horizontal frequency for convergence and Z axis
correction address generator clocking. (TP 20)
/CORSTRT
Signal used to start the convergence and overlay address
generators during each horizontal sweep. (TP 4)
/FRAMEST
Indicates the beginning of a frame. Used in the SCB for
counting vertical frequency. (TP 5)
INTI
Indicates when input source signal is interlaced. (TP 2)
/VSYNCSC
Regenerated vertical sync signal, pulse shaped to 3 horizontal
lines in width. (TP 7)
/FIELD1
Low during field #1 of an interlaced input source. (TP 8)
/MAPST
Pulse signal to signal the overlay and correction address
generators to reset for a new frame. (TP 12)
I/O
Description
IICDATA
IIC data line. Bi-directional serial line for synchronous data
transfer between SCB and other circuit boards. See detailed
description for list of signals transferred and data direction.
Video Processor Board
Inputs
Description
SGSYNC
Stripped Green Sync is Sync-on-Green composite sync signal.
(TP 10)
HCSYNC
Horizontal/Composite Sync. (TP 9)
VSYNC
Vertical Sync used only for separate H and V sync. (TP 21)
Outputs
Description
DCRSTR
Pulse for DC restore timed to correspond to ST, BP, or TL.
(TP 1)
VIDBLNK
Signal for image blanking from adjustment counters. (TP 6)
/VSYNCSC
Vertical sync signal pulse for ILA bias sync. (TP 7)
Horizontal Deflection Board
Inputs
Description
/HVFLBCK
Signal representing horizontal flyback from the HDB. Used for
determining H phase. (TP 17)
Outputs
Description
/VFBST
Signal to start the vertical retrace. (TP 11)
/HSYNCRE
Selected HSYNC signal. (TP 14)
Vertical Deflection Board
Outputs
Description
/PCST
Signal to time the start of T/B pincushion and linearity
correction. (TP 31)