Projector Service Manual
Table Of Contents
- DECLARATION OF CONFORMITY
- BZSAFE.PDF
- CH1INTRO.PDF
- CH2SYSDE.PDF
- Functional Descriptions
- Contents
- Cover and Base
- External Power Requirements
- Electronics Systems Overview
- System Power
- Card Cage
- Circuit Boards
- Raster Timing Generator Board (RTG) p/n 100568
- Sync Generator
- Sync Detector and Selector
- Serration and Equalization Lockout
- Phase Locked Loop
- VSYNC Detector, Field Separator, and Mux
- Adjustment Counters
- Serial Communication
- Raster Timing Generator I/O
- Interlocks and Protection
- Horizontal Deflection Board P/N 102523 (HDB)
- Vertical Oscillator
- Horizontal Phase Locked Loop
- Horizontal Centering
- Horizontal Power Supply
- Flyback Switching
- Geometric Correction
- Output Section
- Horizontal Sweep Failure Detection
- Serial Communication
- Horizontal Deflection Board I/O
- Interlocks and Protection
- Vertical Deflection Board P/N 102521(VDB)
- Vertical Preamps
- Vertical Amplifiers
- Sweep Failure Detection
- Side Pincushion and Keystone Correction
- Horizontal Linearity Correction
- Top and Bottom Pincushion and Keystone Correction
- Correction Amplifiers
- Serial Communication
- General I/O
- Interlocks and Shutdowns
- Video Processor Board P/N 104672 (VPB)
- Decoder
- Video/Sync Mux
- V & H Sync Strip
- SG Sync Strip
- B, G, and R Brightness and Contrast Amplifiers
- On-Screen Switch
- Gamma Correction
- Switch Logic and Video Enable
- RGB Sensitivity and Threshold Amplifier
- ILA® Bias
- Dynamic Focus Amplifier
- Serial Communication
- General I/O
- Interlocks and Protection
- Video Amplifier Board P/N 103567 or 103774 (VAB)
- Video Signal
- Failure Detection
- Beam Current Sense
- DC Restore
- Arc Protection
- Blanking
- Enable Circuit
- Focus
- Filament Supply
- General I/O
- System Controller Board P/N 104668 (SCB)
- General Functional Description
- CPU
- Working and Compressed Memory
- Expanded Memory
- Correction Address Generator
- DACs
- DSP
- Overlay Memory
- Overlay Address Generator
- Overlay Interface
- LED Display Buffers and Logic
- RS232 Interface
- IR Interface
- IIC Interface
- Serial Interface
- General I/O
- Backplane Board p/n 100571
- Optical Section
- Image Light Amplifier
- Functional Descriptions
- CH3ADJST.PDF
- CH4MAINT.PDF
- Maintenance Remove/Replace)
- Contents
- Introduction
- Projector Covers
- Ventilation Filters
- Arc Lamp Assembly
- System Power Supply
- Electronics Module
- Cathode Ray Tube (CRT)
- Video Amplifier Board (VAB)
- CRT Yoke
- High Voltage Power Supply (HVPS)
- Card Cage (Printed Circuit Boards)
- Image Light Amplifier Assembly
- Projection Lens
- (SCB) Socket Battery Replacement
- Recommended Spares
- Maintenance Remove/Replace)
- CH5TRBSH.PDF
- HGLOSS.PDF

Chapter 2—Functional Description
Model 330, 340SC and 370SC Service Manual 2-23
I
T Blank
Commanded position of top blanking.
I
B Blank
Commanded position of bottom blanking.
I
/STBP
Command for DC restore timing on either
leading or trailing edge of sync pulse.
I
DC Restore Delay
Commanded timing of DC restore after
reference edge of sync pulse.
I
Internal Sync Forced
Command to force internal sync select.
I
Correction Start Delay
Commanded H phase of correction map.
I
Pincushion Start Delay
Commanded H phase of pincushion, keystone,
and linearity correction.
I
2H Sync Enable
Command determines path of H sync signal.
I
Shifted Sync Enable
Command determines path of H sync signal.
O
/External Sync Detect
Is an external sync available.
O
HCount
Count of H lines per frame.
O
/Phase Lock
Indication of PLL lock.
O
Phase Count
Indication of phase difference between
HSYNC and HFlyback.
Raster Timing Generator I/O
This section provides a description of the inputs to and outputs from the RTG. The I/O
description are arranged by the source/destination of the signal and so the assemblies
communicated with are used as the primary heading of each group of signals and then are
further subdivided into inputs and outputs. In each case, the signal's direction is noted,
with input referring to an input to the RTG, and output to an output from the RTG. (e.g.:
under System Controller Board “Input”; SYSCLK refers to the signal SYSCLK that is an
input to the RTG from the System Controller Board). When test points are provided for
the I/O they are noted.
Table 2-5
Raster Timing Generator I/O Signals
System Controller Board
Inputs
Description
SYSCLK
4 MHz clock signal for derivation of internal HDTV sync signal.
(TP 13)
IICCLK
IIC clock line. Unidirectional clock line for control of
synchronous data transfer over IIC data bus.
Outputs
Description
/IICINT
IIC interrupt line. Signal line for slave boards to inform the SCB
(master) that there is data to be transferred. Master then polls
slaves to determine the source of the interrupt.
/Hx224
Square wave signal 224 X the horizontal frequency for overlay
address generator clocking. (TP 23)










