User manual

ATM2 DS3 IQ PIC
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JUNOS 6.1 and laterSoftware release
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Four DS3 ports
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Power requirement: 0.41 A @ 48 V (20.0 W)
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Intelligent queuing (IQ) PICs support fine-grained queuing per logical interface.
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ATM standards compliant
Description
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16-MB SDRAM memory for ATM segmentation and reassembly (SAR)
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ATM switch ID
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Configurable framing options:
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C-bit with ATM direct mapping
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C-bit with Physical Layer Convergence Protocol (PLCP) framing (default)
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M23 ATM direct mapping
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M23 with PLCP framing
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Internal and loop timing
Hardware features
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Per-virtual circuit (VC) and per-virtual path (VP) traffic shaping
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Unspecified bit rate (UBR) traffic shaping
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Fine-grained variable bit rate (VBR) traffic shaping
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Circuit cross-connect (CCC)
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ATM Inverse Address Resolution Protocol (ARP), which enables routers to automatically
learn the IP address of the router on the far end of an ATM permanent virtual circuit
(PVC)
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Simple Network Management Protocol (SNMP):
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Management Information Base (MIB) 2 (RFC 1213)
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ATM MIB (RFC 1695)
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SONET MIB
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AAL5 encapsulations:
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ATM-VC-MUX
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ATM-NLPID
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ATM-Cisco-LLPID
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ATM-SNAP
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ATM-CCC-VC-MUX
Software features
ATM2 DS3 IQ PIC ■ 9
ATM2 DS3 IQ PIC