Data Sheet

Part number:WG7837-V1
Model name :WG7837-V0
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CONFIDENTIAL
7. CLOCK AND POWER MANAGEMENT
The slow clock is a free-running, 32.768 kHz clock supplied from an external clock source. The
clock is connected to the SLOW_CLK pin and is a digital square-wave signal in the range of 0 to 1.8V
nominal
Reset-Power-Up System
After VBAT and VIO are fed to the device and while BT_EN and WL_EN are deasserted (low), the
device is in SHUTDOWN state, during which functional blocks, internal DC-DCs, and LDOs are
disabled. The power supplied to the functional blocks is cut off. When one of the signals (BT_EN or
WL_EN) are asserted (high), a power-on reset (POR) is performed. Stable slow clock, VIO, and VBAT
are prerequisites for a successful POR.
WLAN Power-Up Sequence
Figure 7-1 shows the WLAN power-up sequence.
Figure 7-1. WLAN Power-Up Sequence