User's Manual

Doc No: WG1300BE00 EM Board-UG-R02
Copyright © JORJIN TECHNOLOGIES INC. 2014
http://WWW.JORJIN.COM.TW
CONFIDENTIAL
Page 13
2.4. Schematics
Figure 4 is the schematics of WG1300E00 EM Board
C7
NL_1uF
CAP1608
R16
NL_100K
RES1005
WL_TX
VBAT_SYS
R6
NL_0R
RES1005
To VIO_SYS Host Level
WL_DBG
VBAT_SYS
R19
NL_10K
RES1005
VBAT_SYS
U1
WG1300-B0
E_N51_14.5X14.5_1.3
WL_UAR T_DBG
2
NS_UAR TD
33
WL_EN1
4
WL_EN2
3
WL_RS232_T X
5
WL_RS232_R X
6
EXT_32K
17
GND
36
SCL_CC 3000
24
SCL_EEPROM
23
SDA_CC 3000
26
SDA_EEPROM
25
SPI_IR Q
13
SPI_DOU T
12
SPI_CS
15
SPI_CLK
14
SPI_DI N
11
RF_AN T
35
DC2D C_OUT
30
GND
27
GND
1
GND
9
GND
37
GND
38
GND
39
GND
40
GND
16
VBAT_IN
28
GND
31
GND
7
VIO_SOC
8
GND
19
GND
34
GND
41
GND
42
GND
43
GND
51
GND
50
GND
49
GND
48
GND
44
GND
45
GND
46
GND
47
XTALM
21
XTALP
20
GND
18
GND
29
GND
10
GND
22
CLK_REQ_OU T
32
R23
NL_0R
RES1005
VBAT_SYS: 2.7V~4.8V => 3.6V TYP
VBAT_SYS
VBAT_SW_EN
VIO_SOC: 1.62V~1.92V => 1.8V TYP
WL_RX
WL_DBG
WL_TX
C3
NL_10pF
CAP1005
J1
U.F L-R-SMT(10)
U.FL
1
2
3
L2
2.2nH
IND 1005
C1
2.2pF
CAP1005
L1
NL
IND 1005
C2
10pF
CAP1005
WL_EN1
ANT1
AT8010-E2R9HAA
8.0x1. 0x1.0mm
1
2
VIO_CLK
The Antenna matching circuit.
VBAT_IN
VBAT_IN
U2
SN74AVC2T45
XBGA-N8_1X2_0.5-A
VCCA
1
A1
2
A2
3
GND
4
VCCB
8
B1
7
B2
6
DIR
5
VIO_SOC
VIO LDO
NS_UAR T
U4
SN74AVC2T45
XBGA-N8_1X2_0.5-A
VCCA
1
A1
2
A2
3
GND
4
VCCB
8
B1
7
B2
6
DIR
5
R17 0R
RES1005
WL_SPI_I RQ_1V8
WL_SPI_D OUT_1V8
U5
SN74AVC2T45
XBGA-N8_1X2_0.5-A
VCCA
1
A1
2
A2
3
GND
4
VCCB
8
B1
7
B2
6
DIR
5
WL_SPI_C S_1V8
U6
TPS22913B
XBGA-N4_0.9x0.9_0.5
VIN
A2
VOUT
A1
ON
B2
GND
B1
VBAT_IN
U3
TPS79718
MO-203_2.1x2
GND
2
NC
3
IN
4
OUT
5
PG
1
R9 0R RES1005
VIO_SYS: Voltage of Host Level
WL_SPI_I RQ_HOST
WL_SPI_D OUT_HOST
-->
C6
1uF
CAP1608
R18
100K
RES1005
-->
VIO_SOC
C4
1uF
CAP1608
-->
DIR High : A data to B bus
DIR Low : B data to A bus
VBAT_SYS
R15
100K
RES1005
VBAT_SYS
C5 0.1uF
CAP1005
WL_SPI_C LK_HOST
WL_SPI_D IN_HOST
WL_SPI_C S_HOST
VBAT_SYS FET SWITCH
WL_SPI_C LK_1V8
WL_SPI_D IN_1V8
WL_EN1
DC2D C_OUT
R3
0R
RES1005
J14
Male 1x3
1
2
3
RTTT Debug
VIO_SOC
Networking Subsystem Debug
NS_UAR T
DC2D C_OUT
WL Debug Logger
R4
NL_0R
RES1005
VBAT_IN
VIO_SOC
R1
0R
RES1005
32KHz_1V8_HOST
R7 NL_0R
RES1005
SLOW CLK 32.768KHz
OSC1
SG-3030LC/32. 768kHz
CY -N12_3.6X2.8_0.5
VIO
1
VCC
12
OUT
7
GND
6
NC
2
NC
3
NC
4
NC
5
NC
8
NC
9
NC
10
NC
11
R2
0R
RES1005
J10
Male 1x2
1
2
Connect to Host SPI Interface.
(Host I/O level: VIO_SYS)
Internal Power FET Switch Enable.
Connect to Host GPIO.
VIO_SOC
The 32.768kHz clock select.
Connect to OSC or Host source.
J16
NL_Male 1x3
1 2 3
R14
NL_0R
RES1005
VIO_SOC
C22
10uF
CAP2012
J11
Male 1x2
1 2
Debug mode => 1-2 short to GND
Functional mode => 2-3 short
WL_EN2
VIO_SOC
EM Connector
J12
Male 1x2
1
2
WL_SPI_C S_1V8
R8 0R RES1005
R11 0R RES1005
WL_SPI_I RQ_1V8
R10 0R RES1005
WL_SPI_C LK_1V8
R13 0R RES1005
WL_SPI_D IN_1V8
R12 0R RES1005
WL_SPI_D OUT_1V8
VBAT_SYS
R21 NL_0R
RES1005
32KHz_1V8_HOST
32KHz_1V8_HOST
R20 NL_0R
RES1005
WL_SPI_D IN_HOST
WL_SPI_C LK_HOST
VBAT_SW_EN
WL_SPI_C S_HOST
WL_SPI_D OUT_HOST
WL_SPI_I RQ_HOST
J6
SFM-110-02-L-D-A
pitch 1.27-2x10
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
R5
0R
RES1005
VBAT_SYS
J7
SFM-110-02-L-D-A
pitch 1.27-2x10
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
R22
0R
RES1005
J13
Male 1x6
1
2
3
4
5
6
VBAT_SYS
VBAT_SYS
VIO_CLK: 3.3V
VBAT_IN
Reserved VIO CLK LDO
VIO_CLK
WL_RX
U7
NL_TPS79733
MO-203_2.1x2
GND
2
NC
3
IN
4
OUT
5
PG
1
Figure 4. Schematics of WG1300BE00 EM Board