User's Manual

3. FUNCTIONAL DESCRIPTION
This chapter describes the ESP32-PCIO-V3-02 various modules and functions.
3.1. CPU AND MEMORY
Xtensa®single-/dual-core32-bitLX6microprocessor(s), upto600MIPS
(200MIPSforESP32-S0WD/ESP32-U4WDH, 400 MIPS for ESP32-D2WD):
MCU
 ESP32 embedded, Xtensa® dual-core 32-bit LX6 microprocessor, up to 240
MHz
 • 448 KB ROM
 • 520 KB SRAM
 • 16 KB RTC SRAM
3.2. STORAGE DESCRIPTION
3.2.1. External Flash and SRAM
ESP32 support multiple external QSPI flash and static random access memory
(SRAM), having a hardware-based AES encryption to protect the user programs and
data.
 ESP32 access external QSPI Flash and SRAM by caching. Up to 16 MB external
Flash code space is mapped into the CPU, supports 8-bit, 16-bit and 32-bit
access, and can execute code.
 Up t
o 8 MB external Flash and SRAM mapped to the CPU data space, support
for 8-bit, 16-bit and 32-bit access. Flash supports only read operations, SRAM
supports read and write operations.
3.3. CRYSTAL
Esp32-pico-v3-02 SiP has seamlessly integrated all peripheral components such as
crystal oscillator, Flash, PSRAM, filter capacitor, RF matching link into the package, and
no peripheral components are needed to work.
3.4. RTC MANAGEMENT AND LOW POWER
CONSUMPTION
ESP32 uses advanced power management techniques may be switched between
different power saving modes. (See Table 5).