Product Data Sheet
MF1S50yyX_V1 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 3 March 2014
279230 29 of 40
NXP Semiconductors
MF1S50yyX/V1
MIFARE Classic EV1 1K - Mainstream contactless smart card IC
15. Wafer specification
For more details on the wafer delivery forms see Ref. 9.
[1] The step size and the gap between chips may vary due to changing foil expansion
[2] Pads VSS and TESTIO are disconnected when wafer is sawn.
15.1 Fail die identification
Electronic wafer mapping covers the electrical test results and additionally the results of
mechanical/visual inspection. No ink dots are applied.
Table 32. Wafer specifications MF1S50yyXDUy
Wafer
diameter 200 mm typical (8 inches)
maximum diameter after foil expansion 210 mm
thicknessMF1S50yyXDUD 120 m 15 m
MF1S50yyXDUF 75 m 10 m
flatness not applicable
Potential Good Dies per Wafer (PGDW) 64727
Wafer backside
material Si
treatment ground and stress relieve
roughness R
a
max = 0.5 m
R
t
max = 5 m
Chip dimensions
step size
[1]
x = 658 m
y = 713 m
gap between chips
[1]
typical = 19 m
minimum = 5 m
Passivation
type sandwich structure
material PSG / nitride
thickness 500 nm / 600 nm
Au bump (substrate connected to VSS)
material > 99.9 % pure Au
hardness 35 to 80 HV 0.005
shear strength > 70 MPa
height 18 m
height uniformity within a die = 2 m
within a wafer = 3 m
wafer to wafer = 4 m
flatness minimum = 1.5 m
size LA, LB, VSS, TEST
[2]
=66 m 66 m
size variation 5 m
under bump metallization sputtered TiW