Wiring Diagram

Jiangsu JWT Electronics Shares CO.,Ltd.
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15
TX_EN
R/W
Enable the chip to enter the
sending state, 1 is valid
0
14
RX_EN
R/W
To enable the chip to enter the
receiving state, 1 is valid
Note: TX EN and RX EN cannot be 1
at the same time, while at 0, the
chip is in IDLE state
0
13-12
reserved
R/W
00
11-7
SWALLOW[4:0]
R/W
When RF PLL DIIRECT= 1, the
carrier frequency is set directly by
the register：
RF={reg0[6:0],reg0[13:9]}
00000
6-0
RF_PLL_CH_NO[6:
0]
R/W
When RF PLL DIIRECT= 0, the
carrier frequency is set by the
channel number：
RF=2402+RF_PLL_CH_NO[6:0]
110000
f=2450MHz
Table 11-1
Miscellaneous configuration Register 0x01 default: 0x2077
Bit
Name
R/W
Description
Default
15
Sleep_mode
R/W
Enable the chip to enter the sleep
mode, 1 is valid （ SPI CS must
maintain high level simultaneously）
0
14
R/W
0
13
CRC_EN
R/W
0: CRC close 1: CRC open
1
12
11
10
RF_PLL_DIRECT
R/W
RF_PLL_DIIRECT=1
RF={reg0[6:0],reg0[13:9]}
otherwise
RF=2402+RF_PLL_CH_NO[6:0]
0
9
Pkt_hint_pority
R/W
1: PKT/FIFO flag Low effective
0: PKT/FIFO flag High effective
0
8
Miso_tri_opt
R/W
0: SPI_CS=1 time SPI_MISO For
high impedance output
1: SPI_CS=1 time SPI_MISO For low
level output
0
7
Reset_system
W/R
1 ： Enable the chip to perform
software reset
Note: reg0x1e[0] must be put 1
0