Wiring Diagram

Jiangsu JWT Electronics Shares CO.,Ltd.
12 / 45
SPI Timing requirements
I2C interface
I2C command format
Master writes one or more bytes to FIFO or Register
Master writes a byte to the designated register, and then reads 1 or more bytes of data from
the FIFO
Master can continuously read FIFO data
Name Min Typ. Max Description
T
1
250ns Time interval between two SPI
visits
T
2
41.5ns Time interval between SPI_CS and
SPI_CLK
T
3
Note.1 Address and date interval
T
4
Note.1 The interval time between the high
byte and the low byte
T
5
Note.2 Interval time between two registers
T
6
83ns Clock cycle of SPI
Picture10-1