Wiring Diagram

Jiangsu JWT Electronics Shares CO.,Ltd.
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PLL_stable
PLL Settling time
150
us
code rate
1
Mbps
FCH 1M
Channel spacing
1
MHz
Emission pattern index
PRF
maximum power
output
8
dBm
PRF
Typical output
0
dBm
PRFC
Output Power Range
-24
8
dBm
PBW1
Carrier modulated
20dB Mbps（1Mbps）
1
1.1
MHz
Receiving mode index
RXSENS2
receiving sensitivity
（0.1%BER）
-89
dBm
Immunity characteristics
C / Ι CO
Co-channel
Interference
9
dBc
C / Ι1ST
Phase 1 lead
interference
5
dBc
C /Ι2ND
Phase 2 lead
interference
-12
dBc
C / Ι 3RD
Phase 3 lead
interference
-24
dBc
operating conditions
VDD
Power Supply
1.9
3
3.6
V
VSS
processing chip.
0
V
VOH
high -level output
voltage
VDD-0.3
VDD
V
VOL
Low Level Output
Voltage
VSS
VSS+0.3
V
VIH
high-level input
voltage
2.0
3
3.6
V
VIL
Low Level Input
Voltage
VSS
VSS+0.3
V
Cin
input capacitance
10
pF
Working
Temperature
-10
27
+50
℃
Storage Temperature
-20
27
+70
℃
Table 2-2
Notes: 12MHz The load capacitance of the crystal oscillator is 8.2pF