Wiring Diagram

Jiangsu JWT Electronics Shares CO.,Ltd.
16 / 42
Rx_ack_time[5:0]
（More than this time, if you haven't
received an ACK signal back, it will
automatically resend）
Table 11-6
Timing configuration Register 0x0c default: 0x3E11
Bit
Name
R/W
Description
Default
15-10
VCO_ON_DLY[5:0]
R/W
After starting TX/RX state, wait for
VCO to stabilize time：
000000: 4us
000001: 8us
.........
111111: 256us
001111
9-8
TX_PA_OFF_DLY[1:
0]
R/W
PA OFF-Delay：
00: 4us
01: 6us
10: 8us
11: 10us
10
7-4
TX_PA_ON_DLY[3:
0]
R/W
PA Open the time delay：
x000: 4us
x001: 8us
....
x1111: 32us
0001
3-0
TX_SW_ON_DELAY
[3:0]
R/W
TX_SW Open the time delay：
0000: 8us
0001: 12us
....
11111: 68us
0001
Table 11-7
RSSI value Register 0x11 Read only
Bit
Name
R
Description
Default
15-8
RAW_RSSI[7:0]
R
8 bit RSS value（Update in real time
and keep maximum value）
7-0
rssi_lat[7:0]
R
RSSI latch
Table 11-8
Block status Register 0x12 Read only
Bit
Name
R
Description
Default
Optium