Wiring Diagram

Jiangsu JWT Electronics Shares CO.,Ltd.
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to read a pointer, the chip
automatically ends the TX state
0
SCRAMBLE_EN
R/W
0: scramble off 1: scramble on
1
Table 11-2
PA Power Control Register 0x02 default: 0x4060
Bit
Name
R/W
Description
Default
15-12
reserved
R/W
0011
11-8
reserved
R/W
rev
0000
7-4
reserved
R/W
1000
3-0
PA_PW_SET[4:0]
R/W
PA output power control：
1111: min
1000: med
0000: max
0000
Table 11-3
Operation configuration Register 0x03 default: 0x5800
Bit
Name
R/W
Description
Default
15-13
Preamble_len[2:0]
R/W
000: 1 byte, 10101010
001: 2 byte, 10101010 10101010
111: 8 byte, 10101010 .............
010
12-11
Syncword_len[1:0]
R/W
00: 16 bits,{reg31[15:0]}
01: 32 bits, {reg31[15:0],
reg34[15:0]}
10: 48 bits, {reg31[15:0],
reg33[15:0], reg34[15:0]}
11: 64 bits, {reg31[15:0],
reg32[15:0], reg33[15:0],
reg34[15:0]}
11
10-8
Trailer_len[2:0]
R/W
000: 4 bits, 1010
001: 6 bits, 101010
.......
111: 18 bits,101010......101010
000
7-6
Data packet
type[1:0]
R/W
00: NRZ law data
01:Manchester data type
10: 8/10 line code
11: interleave data type
00
5-4
FEC type[1:0]
R/W
00: No FEC
01: FEC 13
10: FEC 23
00