Wiring Diagram
Jiangsu JWT Electronics Shares CO.,Ltd.
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Name Min Typ. Max Description
T1 250ns Interval between two SPI visits
T2a,T2b 41.5ns Interval between SPI_CS and SPI_CLK
T3 Note1 Address and data interval
T4 Note1 High byte and low byte interval
T5 Note2 Interval between two registers
T6 83ns Clock cycle of SPI_CLK
Notes:
1. In the FIFO data in the access register 0x28, the chip needs 450ns to find the correct
pointer address read by FIFO.
2. When reading FIFO data in register 0x28, at least wait for 450ns. When reading other
registers, T5min=41.5ns
Eleven．Partial register description
RF Synthesizer TX/RX control Register 0x00 default : 0x0030
Bit
Name
R/W
Description
Default
15
TX_EN
R/W
Enable the chip to enter the
sending state, 1 is valid
0
14
RX_EN
R/W
To enable the chip to enter the
receiving state, 1 is valid
Note: TX EN and RX EN cannot be 1
at the same time, while at 0, the
chip is in IDLE state
0
13-12
reserved
R/W
00
11-7
SWALLOW[4:0]
R/W
When RF PLL DIIRECT= 1, the
carrier frequency is set directly by
the register：
00000
picture 10-2