Specifications
Table Of Contents
www sziton com
RW6852S-50
V1.2 - May, 2022
. .
VDD18
( NP)
4
4 . Application and Implementation
4.1 Application Diagram
ANT0
IPEX
GND GND
C53 NP
R20
C52 NP
R4 8 10K VDDIO
RF_ BT
GND
G_ BT
SD_ RESET
WL_ WAKE_ HOST
SDIO_ CMD
SDIO_ CLK
SDIO_ DATA3
SDIO_ DATA2
SDIO_ DATA0
SDIO_ DATA1
GND
NC
NC
LGA_ 1315
VDDIO
C65 C66
VBAT R18 0R VDDIO
1
VIN
2
GND
3
C50
NP
VDDIO Configuration
Part VDDIO=3.3V
R18 0R
U3 NC
C49 NC
C50 NC
VDDIO= 1.8 V
NC
RT9078
1uF
1uF
0 . 1 u F 10u F
UART Configuration(H4&H5 Protocal)
Part
H4
H5
R43
0R
NC
R44
NC
0R
Suggest:Use H5 Protocal
Figure 3. Application Schematic Diagram of RW6852S-50
ITON Technology Corp.
Page 19 of 22
_
SDIO D1 R30 0R 22
VDDIO
R29 2 .2K
GND
45
RW6852S-50
G_WL
44
R46 10K
_REG_ON
UART_RXD
R42 47K
VDDIO
41 R41 0R UART_RX
UART_RTS_N
R44 0R/NC
RW6852S-50B2
UART_ CTS_N
_
VDDIO R33
SDIO_ CLK R39 0R
VDDIO R34
SDIO_D3 R36 0R
VDDIO R35
SDIO_D2 R37 0R
VDDIO R28
SDIO_D0 R31 0R
SDIO CMD 17
BT_REG_ON
R45 10K
VDDIO
48
49
HOST_WAKE_BT
GND
HOST_ WAKE_ BT
R47 10K
VDDIO
GND
40 R40 0R UART_TX
38 BT_REG_ON
C62
C59
C60
C58
2 .2K
2 .2K
2 .2K
2 .2K
47 SUSCLK
VDDIO R32 2 .2K
BT_ WAKE_ HOST
18
19
20
21
R22 4 .7K
R19
WL_ REG_ ON
12
C64 C63
UART_ TXD
R21
10p F
5.6p F25
23
24
C51 NP
C54 NP
NP
GND GND
GND GND
EN NC
U3 RT9078
ANT2
IPEX
ANT1
IPEX
NC
10p F
10p F
SUSCLK
13
46
39
F F
VOUT
VBAT
C61
C57
C56
C49
C55
37
14
NP
NP
5
50
BT_WAKE_HOST
5.6 p F5 .6 p 5 .6 p 5 .6 p F5 .6 p F
4.7 u F 0 . 1 u F
VDD33
VDDIO
SD_RESET 15
VDDIO
WL_WAKE_HOST
R23 10K
16