Data Sheet

Page 48
nRF51822 Product Specification v3.1
8.3 Block resource requirements
Table 33 Clock and power requirements for different blocks
8.4 CPU
Table 34 CPU specifications
Block ID
Resource requirements
Comment
1V2
HFCLK
1
1. HFCLK could be one of the following; RC16M, XO16M, or XO32M.
LFCLK 1V7
Radio 1 x x Requires HFCLK XOSC.
UART 2 x x
When receiver or transmitter are
STARTed.
SPIS 4 x x Requested when CSN asserts.
SPI 3, 4 x x
TWI 3, 4 x x
GPIOTE 6 x x Only in input mode.
ADC 7 x x Requires HFCLK XOSC.
TIMER 8, 9, 10 x
Requires 1V2 when a TIMER EVENT is
triggered.
RTC 11, 17 x
HFCLK will be requested if the LFCLK is
synthesized from HFCLK.
TEMP 12 x x Requires HFCLK XOSC.
RNG 13 x x
ECB 14 x x
WDT 16 x
HFCLK will be requested if the LFCLK is
synthesized from HFCLK.
QDEC 18 x x
LPCOMP 19 No resources required.
CPU -- x x x
Symbol Description Min. Typ. Max. Units
Test
level
I
CPU, FLASH
Run current at 16 MHz (XOSC).
Executing code from flash memory.
4.1
1
1. Includes CPU, flash, 1V2, 1V7, RC16M.
mA 2
I
CPU, RAM
Run current at 16 MHz (XOSC).
Executing code from RAM.
2.4
2
2. Includes CPU, RAM, 1V2, RC16M.
mA 1
I
START, CPU
CPU startup current. 600 µA 1
t
START, CPU
IDLE to CPU execute.
0
3
3. t
1V2
if 1V2 regulator is not running already.
µs 1