Data Sheet

Page 45
nRF51822 Product Specification v3.1
Power on reset time (t
POR
) is the time from when the supply starts rising to when the device comes out of
reset and the CPU starts. The time increases with, and is inclusive of, supply rise time from 0 V to VDD.
Table 30 gives t
POR
for a number of supply rise times, simulated with a linear ramp from 0 V to VDD, over the
supply voltage range 1.8 V to 3.6 V.
Table 30 Power on reset time
The data in Figure 10 and Table 31 show measured t_
POR
data. Measurements were taken using the
reference circuit shown in Section 11.3.1 “QFAA QFN48 schematic with internal LDO setup” on page 79 with
the given supply voltage and temperature conditions.
Figure 10 Power on reset time (Test level 2)
Table 31 Supply rise time at sample voltages for the measured data shown in Figure 10.
Symbol Description Note Min. Typ. Max. Units
Test
level
t
POR, 10 µs
Power on reset time, 10 µs rise
time (0 V to VDD).
0.7 2.4 19 ms 1
t
POR, 1 ms
Power on reset time, 10 µs rise
time (0 V to VDD).
1.7 3.4 20 ms 1
t
POR, 10 ms
Power on reset time, 10 µs rise
time (0 V to VDD).
11 12 28 ms 1
t
POR, 100 ms
Power on reset time, 10 µs rise
time (0 V to VDD).
68 101 115 ms 1
VDD Rise Time from 10% to 90% of VDD
1.8 570 µs
3.0 605 µs
3.6 635 µs