Data Sheet

Page 24
nRF51822 Product Specification v3.1
3.4.2 Power management
The power management system is highly flexible with functional blocks such as the CPU, Radio Transceiver,
and peripherals having separate power state control in addition to the global System ON and OFF modes. In
System OFF mode, RAM can be retained and the device state can be changed to System ON through Reset,
GPIO DETECT signal, or LPCOMP ANADETECT signal. When in System ON mode, all functional blocks will
independently be in IDLE or RUN mode depending on needed functionality.
Power management features:
• Supervisor HW to manage
•Power on reset
•Brownout reset
• Power fail comparator
• System ON/OFF modes
• Pin wake-up from System OFF
•Reset
• GPIO DETECT signal
• LPCOMP ANADETECT signal
• Functional block RUN/IDLE modes
• RAM retention in System OFF mode (8 kB blocks)
• 16 kB version will have 2 blocks
• 32 kB version will have 4 blocks
3.4.2.1 System OFF mode
In system OFF mode the chip is in the deepest power saving mode. The system's core functionality is
powered down and all ongoing tasks are terminated. The only functionality that can be set up to be
responsive is the Pin wake-up mechanism.
One or more blocks of RAM can be retained while in System OFF mode.