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nRF51822 Product Specification v3.1
3.2 Memory
All memory and registers are found in the same address space as shown in the Device Memory Map, see
Figure 5. Devices in the nRF51 series use flash based memory in the code, FICR, and UICR regions.
The RAM region is SRAM.
Figure 5 Memory Map
The embedded flash memory for program and static data can be programmed using In Application
Programming (IAP) routines from RAM through the SWD interface, or in-system from a program executing
from code area. The Non-Volatile Memory Controller (NVMC) is used for program/erase operations. Regions
of flash memory can be protected from read, write, and erase by the Memory Protection Unit (MPU). A User
Information Configuration Register (UICR) contains the lock byte for enabling readback protection to secure
the IP, while individual block protection is controlled using registers which can only be cleared on chip reset.