Datasheet

IR2121 & (PbF)
8 www.irf.com
Figure 14A. Logic “1” Input Threshold vs. Temperature Figure 14B. Logic “1” Input Threshold vs. Voltage
Figure 13B. CS to ERR Pull-Up vs. VoltageFigure 13A. CS to ERR Pull-Up vs. Temperature
Figure 15A. Logic “0” Input Threshold vs. Temperature Figure 15B. Logic “0” Input Threshold vs. Voltage
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "1" Input Threshold (V)
Min.
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
V
CC
Logic Supply Voltage (V)
Logic "1" Input Threshold (V)
Min.
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "0" Input Threshold (V)
Max.
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
V
CC
Logic Supply Voltage (V)
Logic "0" Input Threshold (V)
Max.
0.0
4.0
8.0
12.0
16.0
20.0
10 12 14 16 18 20
V
BIAS
Supply Voltage (V)
CS to ERR Pull-Up Delay Time (µs)
Max.
Typ.
0.0
4.0
8.0
12.0
16.0
20.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
CS to ERR Pull-Up Delay Time (µs)
Max.
Typ.