User Manual

SECTION 1: THEORY OF OPERATION
~\Technical Documentation\System Manuals\FCC-Reports\IP1HPV\IP1HPV-FCCRpt.doc Page 5

IP1 HPV Data Transceiver Section Descriptions
The IP1 Data Transceiver works within a frequency range of 135 to 175 MHz.
This section provides detailed descriptions of each of the sections within the IP1 HPV Data Transceiver.
Refer to Appendix A to view the IP1 HPV Data Transceiver Circuit Board Diagram.
Microcontroller
The microcontroller (U30) is a major component of the radio as it manages the operation of the radio
loading the selected transmit/receive frequencies into the injection sythesizer. It also controls the
operation of the modem, and determines which receiver provides a better signal from a given
transmission. It provides transmit time-out protection in the event a fault causes the radio to halt in the
transmit mode. It utilizes a reduced instruction set computer (RISC) architecture which provides low
power operation and a powerful instruction set. Other features include a watchdog timer, serial UART,
two 8-bit timers, and 2 KB of electrically erasable programmable read only memory (EEPROM) storage.
NOTE
: The EEPROM RAM stores the setup data entered by the technician even if there is a loss of
power.
Support circuitry
The support circuitry consists of the following:
 A Supervisor Control Chip (U25) provides power-on reset.
 The clock controls microcontroller operation and is generated by crystal Y3 and a Pierce oscillator
circuit (inside the U30-microcontroller).
 The latch (U28) decodes low order address bits (A0-A7) from the address/data bits (AD0-AD7). It is
controlled by Address Latch Enable (ALE) output of U30 and the bits are used by the modem and
synthesizer circuitry.
 A 512Kx8 Static RAM Chip (U31) provides temporary storage of the radio’s configuration data
facilitating the technician with access to make changes.
 Glue logic, also an important part in the microcontroller section. The RAM chip select (CS) and
modem chip select (MODEMCS*) command lines are created by U26ABC, U27BCD, and U29ABC.
These gates decode four (4) high order address bits (A11-A15), plus the read (RD*) and write (WR*)
command lines. The RAM is addressed by five (5) memory addresses (MA14-MA18) bits decoded by
U26D, U27A, and U24. This logic decodes port address bits (PA14-PA18) to produce memory
address bits (MA14-MA18) for the RAM chip.
Input/Output
Input/output components convert serial and handshake data from the modem section to RS232 levels,
and vice-versa. Chip U22 is an RS232 transmitter and receiver. It converts data in 5-volt logic form to
data in +/-12-volt form, as required by the RS232 standard. A charge pump power supply on the chip
converts the +5-volt DC logic power on pin 26 to the +12-volt and –12-volt levels required. Capacitors
C106-C109 generate these voltages by a charge pump. These values determine the operating voltages.
This section also includes DIP switch (S1) and an octal tri-state buffer (U23). S1 provides hardware
programming for external modulation. U23 is used only in MDT-870 applications. When enabled by S1