User's Manual

F32700N25.doc Page 7
The microcontroller section controls the modem operation. Address bus, address/data
bus, and control lines operate the modem chip. The modem circuitry is also run by a
crystal-controlled clock, which consists of crystal Y1 and an internal Pierce oscillator.
The received audio signal is demodulated into digital data appearing on the AD0-AD07
lines when the MODEMCS* and RD* lines are low. The data goes to the
microcontroller section for futher processing, and then to the input/output section for
conversion to RS232 or Ethernet signal levels.
During a transmission, outgoing data appearing on the AD0-AD07 lines is converted
into a 4-level FSK analog signal by the modem chip. This operation takes place when
the MODEMCS* and WR* lines are low. Data from the user’s DTE passes through the
input/output section and microcontroller section to the AD0-AD07 bus. After processing,
data passes through a root raised cosine filter and is output to TXMOD.
This modem supports 115.2 KBPS (serial port) and 32 KBPS (over-the-air) data
transmission rates.
VLogic and Digital Ground
The VLogic and Digital Ground section consists of a pulse-width modulation (PWM)
step-down DC-DC converter (U20) that provides an adjustable output. It also reduces
noise in sensitive communications applications and minimizes drop out voltage.
An external Schottky diode (D2) is required as an output rectifier to pass inductor
current during the second half of each cycle to prevent the slow internal diode of the N-
channel MOSFET from turning on. This diode operates in pulse-frequency modulation
(PFM) mode and during transition periods while the synchronous rectifier is off.
Receiver Front-End
This section contains components that include several RF Band-pass filters, a low-noise
amplifier, and a MMIC mixer.
Incoming signals pass through one (1) pre-selector filter (FLT3) that selectively provides
a high degree of out-of-band signal rejection. A low MMIC amplifier (U4) amplifies the
selected signals and is followed by an image and noise reject filter (FLT6). The output
from FLT6 passes through a gain stage amplifier (U7) then passes through a mixer
(U8). U8 is a MMIC mixer which mixes the receive injection (RXINJ1) signal from the
synthesizer and the RF signal from the antenna to produce a 45 MHz IF signal. This 45
MHz signal passes through crystal filters (FLT3 and FLT4) to the Receiver IF section to
provide the bulk of the Receiver’s selectivity.