User Manual
SECTION 1: THEORY OF OPERATION
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IF Amplifier
The incoming 45 MHz signal passes through Y5, a highly selective monolithic bandpass filter. From there
the IF signal passes through an LC matching network. C17, C18, C24, and L5 provide impedance
matching to the IF amplifier input. U6 is a super heterodyne IF subsystem. Inside the chip, the signal is
applied to a mixer. The mixer also accepts a 44.545 MHz local oscillator input. The local oscillator
consists of an internal amplifier, plus crystal (Y4) and associated components. The mixer output passes
through Y3, a 455 KHz ceramic IF filter. It is amplified, passed through ceramic filter (Y2), and on to a
second IF stage. The IF output drives a quadrature detector. The recovered audio appears at pin 9,
while RSSI appears at pin 7.
Within the RSSI circuitry, chip U6 uses a detector, which converts if the current is generated inside the
chip into a DC level corresponding logarithmically to signal strength. RSSI is used by the Diversity
Reception Controller to select the receiver with the highest quality signal.
The audio is buffered by op amp U3A. From there the AUDIO output line goes to a connector, for hookup
to the Diversity Reception Controller Board.
The RSSI is buffered by op amp U3B. From there the RSSI output line goes to a connector, for hookup
to the Diversity Reception Controller Board.
Several sets of 455 KHz IF filters (Y3 and Y2) are available to suit receiver selectivity requirements.
Should replacement of these filters be required, exact replacement parts must be used.
Receiver Injection
The Injection Synthesizer Board provides a highly stable local oscillator signal for the three receivers. A
synthesizer on the board develops the signal.
This displays a serial data input/output interface, synthesizer, and VCO. The I/O interface circuitry
accepts clock, serial data, and enable signals from the System Controller Board via terminal block TB1. A
lock detect (LD) status output is returned to the System Controller Board from the synthesizer. U3 is a
hex Schmidt Trigger inverter, which squares up incoming signals for reliable operation of the synthesizer
chip. This is necessary because of a cable run between the two (2) boards.
The main section of this board is synthesizer chip (U2). The device contains the key components of a
phase locked loop (PLL), including a 1.1 GHz prescaler, programmable divider, and phase detector. In
operation, the desired frequency is loaded into U2 as a clocked serial bit stream via the CLK and DATA/I
inputs. The lock detection circuitry consists of inverters U3E/U3F, diode CR3, and resistor R5. When the
synthesizer is in lock, the LD pin on U2 is high, making the LD output on terminal block TB1 high. The
EXC LD input on TB1 routes the lock detect output from the Exciter Board through diode CR3, and out
through LD. This configuration tells the CPU on the System Controller Board that it is acceptable to
process received data, or to key the transmitter when LD is high. Otherwise, if a fault in either synthesizer
prevents a lock, receive and transmit operation will be inhibited.
The UHF injection signal is generated by module VCO1. This device is a wide-range voltage controlled
oscillator (VCO). A voltage on the VT input determines the VCO frequency. The voltage is generated by
the phase detector output (PD/O) of U2, which drives a loop filter consisting of R4, C19, C20, R21 and
C10. The filter integrates the pulses, which normally appear on PD/O into a smooth DC control signal for
the VCO. The output of VCO1 is attenuated by module AT1, resulting in improved VCO stability.