User Manual
SECTION 1: THEORY OF OPERATION
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DR4B Base Station Data Radio Circuitry
The DR4B Base Station Data Radio works within the frequency range of 400-512 MHz.
The following section provides detail views, descriptions, and key areas on the DR4B Base Station Data
Radio circuit board especially useful during troubleshooting.
System Controller
This section displays the Central Processing Unit (CPU)(U1), clock, and power-on reset circuitry. It
provides more processing power than required for future capabilities to be incorporated into the radio
without changing processors. Such capabilities include data encryption/decryption (DES), remote fault
monitoring, etc. U1 features a 16-bit address bus and 128K of internal flash random access memory
(RAM). To enter the programming mode it is necessary to reset the switch (S1) and power up again.
CPU operations are controlled by Y2 an 4.9152 MHz clock module. Capacitor (C1) and an internal
Schmidt trigger circuit inside of U1 generates the power on reset signal. The RESET* output from U1
drives a latch and decoder found elsewhere on the board.
This section displays the RAM, decoder, EEPROM, and programming power supply circuitry. U2 is a
512K x 8 bit static RAM chip, which provides temporary storage of radio configuration data while the
power is on. This is necessary in order to program the radio configuration. U2 is controlled directly by the
address, data, and control busses from the CPU.
Chip U5 decodes the A11-A14 address bus to provide chip selects for the modem and EEPROM
memory. Chip U6 is an 8-bit latch. It latches inputs from the D0-D7 bus and lights the front panel status
indicators (
TX, CD, RX1, RX2, and RX3).
Chip U3 is a serial EEPROM, which provides 2K bits of pre-programmed data storage for the CPU. Data
is clocked out of U3 by EECLK, and back into the CPU via EEDATA.
A programming power supply is required for the flash RAM inside of the CPU, and this function is
performed by U4. This chip is an adjustable voltage regulator with a shutdown control. Resistors R8 and
R9 set the output voltage. When the radio configuration data is to be stored in flash RAM, the CPU
makes VPP_ENABLE high. This turns on the regulator, producing a 12-volt output via VPP for the flash
RAM.
This section displays a dedicated processor and voltage regulator. Chip U7 is an optional processor,
which permits manual keyboard operation of the radio. It is not used, and may not be installed on the
board. Regulator U10 provides 5 volts DC power for all logic circuitry on the System Controller Board.
Input/Output
This section displays the CPU input/output circuitry. Chip U11 is an RS232 transmitter/receiver, which
interfaces the CPU to the Diversity Reception Board via J6. From there, the RS232 data goes directly to
a rear panel DB25 connector. U11 converts 5-volt logic-level data to +/-12 volt data in RS232C form, and
vice-versa. A charge pump power supply on the chip converts the +5 volt DC power to the +/-12 volt
levels required. The charge pump uses capacitors (C28 to C31) to generate voltages.
The RS232 serial port data transmission rate of the base station is 115.2 KBPS.