Product Description

nanoBTS Product Description Software Implementation (informative)

6.3 Interprocessor Communications

Secure communications within the nanoBTS are implemented as follows

BH to TRX

HDLC framing including checksum generation and checking

performed in MPC855T and FPGA

Intra-TRX (GSM L2) Messages carried and routed through the FPGA

ARM7 to DSP Dual-port memory interface

ARM7 to Synthesiser

programming registers

DMA

6.4 Process Scheduling

For software tasks running on the ARM7 and MPC855T cores, software processes are

scheduled either

• Asynchronously by the OS running on that processor, or

• Synchronously from interrupts generated by the underlying hardware devices or DSP

Software tasks running on the DSP are scheduled synchronously and deterministically

using interrupts generated by the TCU. DSP tasks are divided into frame-based and

block-based tasks. Frame based tasks have the highest priority, and include

• Burst data read and write

• Modulation and demodulation

• Equalisation, channel decode and deinterleave

• Receiver gain control

• Synthesiser programming

• Transmitter dynamic power control

Note that frame-based tasks occur every timeslot boundary.