Product Description

nanoBTS Product Description Software Implementation (informative)
© ip.access Ltd Page 39
The MPC855T device runs the Nucleus operating system which includes TCP, UDP, IP,
ICMP, SNMP, and all MPC855T device drivers (as part of the Board Support Package).
Other application code is developed internally by ip.access, written in ANSI C.
The FPGA is responsible for managing interprocessor communications buffers. An HDLC
controller is implemented within it, which communicates directly to a similar sub-system in
the MPC855T.
The FPGA also implements GSM frame level synchronisation between the three
ADmsp430 devices.
6.2 Functional Partitioning
Broadly speaking, the GSM air interface functionality is managed by the three ADmsp430
devices, designated the ULM (uplink master), ULS (uplink slave) and DLP (downlink
processor). These are collectively known as the TRX. The Ethernet interface is managed
by the MPC855T, designed the BH (backhaul) processor.
The major functional elements within the nanoBTS are partitioned as follows
Function and sub-function Processor
Even slots ULM
GSM L1 Receive, including
soft-decision equalisation,
de-interleave, channel
decoding and deciphering
Odd slots ULS
GSM L1 transmit, including
ciphering, channel coding,
interleave
All slots DLP
GSM L2 processing,
including BCCH scheduling
DLP
GPRS PCU RLC/MAC BH
GPRS L1 TRX
GPRS Gb BSSGP and NS/IP BH
Operations and
Management Link (OML)
Processing
Abis/IP messages terminate
in the BH and generate
device driver calls as
required
BH
RSL (GSM8.58) messages BH
Radio Signalling Link (RSL)
Processing
Embedded GSM4.08
messages
TRX (for onward
transmission to MS)
Non-volatile storage BH
Code download
management
BH
IP stack and applications
DHCP, ICMP, TCP, RTP,
RTCP, UDP
BH