Product Description

nanoBTS Product Description Hardware Specification
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3.2.4 TRX Baseband Sub-System
Processors Msp430 (3-off: ULM, ULS DLP) 139/140/178: ARM
139/140/178: DSP
Memory ULM SRAM 256k x 16 bit (3 wait state)
ULS SRAM 256k x 16 bit (3 wait state)
DLP SRAM 256k x 16 bit (3 wait state)
3.2.5 Transmitter
Frequency Range Maximum o/p power
139_ (DCS 1800) 1805-1880MHz +23dBm
140_ (PCS 1900) 1930-1990MHz +23dBm
177_ (GSM 850) 869-894MHz +20dBm
178_ (EGSM 900) 925-960MHz +20dBm
165A (DCS 1800) 1805-1880MHz +23dBm, +13dBm (8PSK)
165B (PCS 1900) 1930-1990MHz +23dBm, +13dBm (8PSK)
165C (EGSM 900) 925-960MHz +23dBm, +13dBm (8PSK)
165D (GSM 850) 869-894MHz +23dBm, +13dBm (8PSK)
165E (DCS 1800) 1805-1880MHz +23dBm, +13dBm (8PSK)
165F (PCS 1900) 1930-1990MHz +23dBm, +13dBm (8PSK)
165G (DCS 1800) 1805-1880MHz +23dBm, +13dBm (8PSK)
165H (PCS 1900) 1930-1990MHz +23dBm, +13dBm (8PSK)
Channel spacing 200 kHz
Static power control 6 steps (2dB each)
Dynamic power control 6 steps (2dB each)
Power level error signal Single bit – signals PA loop out of lock
OPLL unlock indicator Single bit - s/w detects unlocked condition
Note that in static power applications (single TRX and C0 carrier) the dynamic power steps
can be used statically to give a total static power control range of 12 steps of 2dB each.