Users Manual

PN17TR 915MHz Transceiver Module Inventis Technology Pty Ltd
Unit 4, 2 Southridge St. Eastern Creek NSW, Australia Page 2
3 Transceiver State Diagram
After initial setup of registers for desired behavior, the normal operation flow diagram is shown as follows. In
applications of infrequent data transmissions the transceiver would be in “sleep” mode to save power (400nA).
From there it would be woken up and enter “idle” mode. As part of the wake up process the crystal oscillator is
started (~240µS) and the digital microcontroller interface is powered up. Before transmit or receive the
frequency synthesizer needs to be started (“FS Wakeup”) and having been powered off (or idle for a while) the
control loop of the VCO/PLL needs to be calibrated (“calibrate”).
A data frame is loaded into the transmit FIFO and the “TX” mode is entered. The transceiver will transmit the
data and enter “idle” mode after completion. When transmit is complete “RX” mode is entered to wait for the
acknowledge frame. Once a frame is received the transceiver will again enter “idle” mode. If no acknowledge
frame is received within a given timeout the data frame would be transmitted. After the last data has
successfully been transmitted the transceiver would again be put in “sleep” mode.