Users Manual

PN17TR 915MHz Transceiver Module Inventis Technology Pty Ltd
Unit 4, 2 Southridge St. Eastern Creek NSW, Australia Page 10
FIFO
0X3C(0xFC)
RCCTRL1_STATUS
Last RC oscillator calibration result
0X3D(0xFD)
RCCTRL0_STATUS
Last RC oscillator calibration result
0x00: IOCFG2 – GDO2 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
R0
Not used
6
GDO2_INV
0
R/W
Invert output, i.e. select active low (1) / high (0)
5:0
GDO2_CFG[5:0]
41 (0x29)
R/W
Default is CHP_RDYn
0x02: IOCFG0 – GDO0 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
TEMP_SENSOR_ENABLE
0
R/W
Enable analog temperature sensor. Write 0 in all other
register bits when using temperature sensor.
6
GDO0_INV
0
R/W
Invert output, i.e. select active low (1) / high (0)
5:0
GDO0_CFG[5:0]
63 (0x3F)
R/W
Default is CLK_XOSC/192 (See Table 41 on page 62).
It is recommended to disable the clock output in
initialization, in order to optimize RF performance.
0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds
Bit
Field Name
Reset
R/W
Description
7
0
Reserved , write 0 for compatibility with possible
future extensions
6
ADC_RETENTION
0
0: TEST1 = 0x31 and TEST2= 0x88 when waking up
from SLEEP
1: TEST1 = 0x35 and TEST2 = 0x81 when waking up
from SLEEP
Note that the changes in the TEST registers due to the
ADC_RETENTION bit setting are only seen INTERNALLY
in the analog part. The values read from the TEST
registers when waking up from SLEEP mode will
always be the reset value.
The ADC_RETENTION bit should be set to 1before
going into SLEEP mode if settings with an RX filter
bandwidth below 325 kHz are wanted at time of
wake-up.
5:4
CLOSE_IN_RX [1:0]
0 (00)
For more details, please see DN010 [8]
Setting
RX Attention, Typical Values
0 (00)
0 dB
1 (01)
6 dB
2 (10)
12 dB
3 (11)
18 dB
3:0
FIFO_THR[3:0]
7 (0111)
Set the threshold for the TX FIFO and RX FIFO. The
threshold is exceeded when the number of bytes in
the FIFO is equal to or higher than the threshold value.
Setting
Bytes in TX FIFO
Bytes in RX FIFO