Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 45
(RD_REQ) from the remote master (master-receiver), at a minimum there should be at
least one entry placed into the slave-transmitter’s TX FIFO.
The I2C Controller is designed to handle more data in the TX FIFO so that subsequent
read requests can take that data without raising an interrupt to get more data.
Ultimately, this eliminates the possibility of significant latencies being incurred between
raising the interrupt for data each time had there been a restriction of having only one
entry placed in the TX FIFO.
This mode only occurs when I2C Controller is acting as a slave-transmitter. If the
remote master acknowledges the data sent by the slave-transmitter and there is no data
in the slave’s TX FIFO, the I2C Controller holds the I2C SCL line low while it raises the
read request interrupt (RD_REQ) and waits for data to be written into the TX FIFO
before it can be sent to the remote master.
If the RD_REQ interrupt is masked, due to bit 5 (M_RD_REQ) of the I2C_INTR_STAT
register being set to 0, then it is recommended that a timing routine be used to activate
periodic reads of the I2C_RAW_INTR_STAT register. Reads of I2C_RAW_INTR_STAT
that return bit 5 (R_RD_REQ) set to 1 must be treated as the equivalent of the RD_REQ
interrupt referred to in this section. This timing routine is similar to that described in
“Slave-Transmitter Operation for a Single Byte”
The RD_REQ interrupt is raised upon a read request, and like interrupts, must be
cleared when exiting the interrupt service handling routine (ISR). The ISR allows you to
either write 1 byte or more than 1 byte into the TX FIFO. During the transmission of
these bytes to the master, if the master acknowledges the last byte, then the slave must
raise the RD_REQ again because the master is requesting for more data.
If the programmer knows in advance that the remote master is requesting a packet of n
bytes, then when another master addresses I2C Controller and requests data, the TX
FIFO could be written with n number bytes and the remote master receives it as a
continuous stream of data. For example, the I2C Controller slave continues to send data
to the remote master as long as the remote master is acknowledging the data sent and
there is data available in the TX FIFO. There is no need to hold the SCL line low or to
issue RD_REQ again.
If the remote master is to receive n bytes from the I2C Controller but the programmer
wrote a number of bytes larger than n to the TX FIFO, then when the slave finishes
sending the requested n bytes, it clears the TX FIFO and ignores any excess bytes.
The I2C Controller generates a transmit abort (TX_ABRT) event to indicate the clearing
of the TX FIFO in this example. At the time an ACK/NACK is expected, if a NACK is
received, then the remote master has all the data it wants. At this time, a flag is raised
within the slave’s state machine to clear the leftover data in the TX FIFO. This flag is