Datasheet

6
FN3158.5
November 16, 2004
The ICM7211AM is intended to accept data from a data bus
under processor control.
In these devices, the four data input bits and the two-bit digit
address (DA1 pin 31, DA2 pin 32) are written into input
buffer latches when both chip select inputs (CS1
pin 33, CS2
pin 34) are taken low. On the rising edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the
contents of the digit address latches.
An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into
D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1.
The timing relationships for inputting data are shown in
Figure 1, and the chip select pulse widths and data setup and
hold times are specified under Operating Characteristics.
1100
1101
1110
1111 BLANK
TABLE 1. OUTPUT CODES (Continued)
BlNARY
CODE B
ICM7211AMB3 B2 B1 BO
a
b
c
d
f
g
e
FIGURE 5. SEGMENT ASSIGNMENT
Test Circuit
FIGURE 6.
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
DIGIT/CHIP
ICM7211AM
DATA
INPUTS
SELECT
INPUTS
V
SS
OSC
V
DD
BP
V
DD
V
DD
V
SS
MICROPROCESSOR
VERSION
MULTIPLEXED
VERSION
EACH SEGMENT
OUTPUT TO
BACKPLANE
WITH A 200pF
CAPACITOR
+ -
V
SS
V
DD
ICM7211AMICM7211AM