Datasheet

4
FN3158.5
November 16, 2004
OSC 36 Floating or with External
Capacitor to V
DD
Oscillator Input
V
SS
Disables BP output devices, allowing segments to be synchronized to an
external signal input at the BP terminal (Pin 5).
Interface Input Configuration
INPUT DESCRIPTION DIP TERMINAL CONDITIONS FUNCTION
DA1 Digit Address
Bit 1 (LSB)
31 V
DD
= Logical One
V
SS
= Logical Zero
DA1 and DA2 serve as a 2-bit Digit Address Input
DA2, DA1 = 00 selects D4
DA2, DA1 = 01 selects D3
DA2, DA1 = 10 selects D2
DA2, DA1 = 11 selects D1
DA2 Digit Address
Bit 2 (MSB)
32 V
DD
= Logical One
V
SS
= Logical Zero
CS1
Chip Select 1 33 V
DD
= Inactive
V
SS
= Active
When both CS1
and CS2 are taken low, the data at the Data and Digit
Select code inputs are written into the input latches. On the rising edge
of either Chip Select
, the data is decoded and written into the output
latches.
CS2
Chip Select 2 34 V
DD
= Inactive
V
SS
= Active
Input Definitions In this table, V
DD
and V
SS
are considered to be normal operating input logic levels. Actual input low and high levels are specified
under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply. (Continued)
INPUT DIP TERMINAL CONDITIONS FUNCTION
Timing Diagram
FIGURE 1. MICROPROCESSOR INTERFACE INPUT
CS1
(CS2)
CS2
(CS1)
DATA AND
DIGIT
ADDRESS
= DON’T CARE
t
DH
t
DS
t
WI
t
ICS
Typical Performance Curves
FIGURE 2. OPERATING SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
FIGURE 3. BACKPLANE FREQUENCY AS A FUNCTION OF
SUPPLY VOLTAGE
V
SUPP
(V)
4123 675
30
25
20
15
10
5
I
OP
(µA)
DISPLAY BLANK, PIN 36 OPEN
T
A
= -20°C
T
A
= 70°C
T
A
= 25°C
V
SUPP
(V)
4123 65
180
150
120
90
60
30
ƒ
BP
(Hz)
T
A
= 25°C
0
C
OSC
= 220pF
C
OSC
= 22pF
C
OSC
= 0pF
(PIN 36 OPEN)
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