Datasheet

ManualsBrandsIntersil ManualsADC - Analog to DigitalA/D converter IC DIL-28

FN3093.3

ICL7135

Digit, BCD Output, A/D Converter

The Intersil ICL7135 precision A/D converter, with its

multiplexed BCD output and digit drivers, combines dual-

slope conversion reliability with ±1 in 20,000 count accuracy

and is ideally suited for the visual display DVM/DPM market.

The 2.0000V full scale capability, auto-zero, and auto-

polarity are combined with true ratiometric operation, almost

ideal differential linearity and true differential input. All

necessary active devices are contained on a single CMOS

lC, with the exception of display drivers, reference, and a

clock.

The ICL7135 brings together an unprecedented combination

of high accuracy, versatility, and true economy. It features

auto-zero to less than 10µV, zero drift of less than 1µV/

input bias current of 10pA (Max), and rollover error of less

than one count. The versatility of multiplexed BCD outputs is

increased by the addition of several pins which allow it to

operate in more sophisticated systems. These include

STROBE, OVERRANGE, UNDERRANGE, RUN/HOLD and

BUSY lines, making it possible to interface the circuit to a

microprocessor or UART.

Features

• Accuracy Guaranteed to ±1 Count Over Entire ±20000

Counts (2.0000V Full Scale)

• Guaranteed Zero Reading for 0V Input

• 1pA Typical Input Leakage Current

• True Differential Input

• True Polarity at Zero Count for Precise Null Detection

• Single Reference Voltage Required

• Overrange and Underrange Signals Available for Auto-

Range Capability

• All Outputs TTL Compatible

• Blinking Outputs Gives Visual Indication of Overrange

• Six Auxiliary Inputs/Outputs are Available for Interfacing to

UARTs, Microprocessors, or Other Circuitry

• Multiplexed BCD Outputs

• Pb-Free Available (RoHS Compliant)

Pinout

ICL7135

(PDIP)

TOP VIEW

Ordering Information

PART NUMBER

TEMP.

RANGE (°C)

PACKAGE

PKG.

DWG. #

ICL7135CPI 0 to 70 28 Ld PDIP E28.6

ICL7135CPIZ

(Note 1)

0 to 70 28 Ld PDIP

(Pb-free) (Note 2)

E28.6

NOTES:

1. Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020C.

2. Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing applications.

V-

REFERENCE

ALOG COMMON

INT OUT

AZ IN

BUFF OUT

REF CAP -

REF CAP +

IN LO

IN HI

V+

(MSD) D5

(LSB) B1

UNDERRANGE

STROBE

R/H

DIGITAL GND

POL

BUSY

(MSB) B8

OVERRANGE

CLOCK IN

(LSD) D1

Data Sheet October 25, 2004

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Summary of content (16 pages)

PAGE 1
ICL7135 ® Data Sheet October 25, 2004 FN3093.3 4 1/2 Digit, BCD Output, A/D Converter Features The Intersil ICL7135 precision A/D converter, with its multiplexed BCD output and digit drivers, combines dualslope conversion reliability with ±1 in 20,000 count accuracy and is ideally suited for the visual display DVM/DPM market. The 2.0000V full scale capability, auto-zero, and autopolarity are combined with true ratiometric operation, almost ideal differential linearity and true differential input.
PAGE 2
ICL7135 Typical Application Schematic SET VREF = 1.000V -5V VREF IN 100kΩ ANALOG GND 0.47µF 100kΩ 27Ω 1µF 100kΩ 28 2 27 3 26 4 25 5 24 6 23 22 7 1µF SIGNAL INPUT 1 8 100K 0.1µF +5V 2 ICL7135 CLOCK IN 120kHz 0V ANODE DRIVER TRANSISTORS DISPLAY 6 21 9 20 10 19 11 18 12 17 13 16 14 15 SEVEN SEG. DECODE FN3093.
PAGE 3
ICL7135 Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical, Note 2) . . . . . . . . . . . . . θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Supply Voltage V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
ICL7135 SET VREF = 1.000V ICL7135 VREF IN 1 V- -5V UNDERRANGE 28 OVERRANGE 27 2 REF 100kΩ 3 ANALOG GND STROBE 26 ANALOG GND 100kΩ RUN/HOLD 25 4 INT OUT 0.47µF 27Ω DIGITAL GND 24 5 A-Z IN 1µF 6 BUF OUT 100kΩ 1µF BUSY 21 8 REF CAP 2 0.1µF +5V 9 IN LO- LSD DI 20 10 IN HI+ D2 19 11 V+ D3 18 12 MSD D5 D4 17 13 LSB B1 MSB B8 16 V+ CLOCK IN 120kHz 7 REF CAP 1 CLOCK IN 22 100K SIGNAL INPUT 0V POLARITY 23 PAD B4 15 14 B2 DIG GND FIGURE 1. ICL7135 TEST CIRCUIT FIGURE 2.
PAGE 5
ICL7135 Detailed Description Analog Section Figure 3 shows the Block Diagram of the Analog Section for the ICL7135. Each measurement cycle is divided into four phases. They are (1) auto-zero (AZ), (2) signal-integrate (INT), (3) de-integrate (DE) and (4) zero-integrator (Zl). Auto-Zero Phase During auto-zero, three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage.
PAGE 6
ICL7135 previous signal was overrange) but no additional STROBE pulses will be sent until a new measurement is available. Digital Section Figure 5 shows the Digital Section of the ICL7135. The ICL7135 includes several pins which allow it to operate conveniently in more sophisticated systems. These include: BUSY (Pin 21) BUSY goes high at the beginning of signal integrate and stays high until the first clock pulse after zero crossing (or after end of measurement in the case of an overrange).
PAGE 7
ICL7135 Digit Drives (Pins 12, 17, 18, 19 and 20) Auto-Zero and Reference Capacitor Each digit drive is a positive going signal that lasts for 200 clock pulses. The scan sequence is D5 (MSD), D4 , D3 , D2 , and D1 (LSD). All five digits are scanned and this scan is continuous unless an overrange occurs. Then all digit drives are blanked from the end of the strobe sequence until the beginning of Reference Integrate when D5 will start the scan again.
PAGE 8
ICL7135 with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3.
PAGE 9
ICL7135 Power Supplies decoder. The 2-gate clock circuit should use CMOS gates to maintain good power supply rejection. The ICL7135 is designed to work from ±5V supplies. However, in selected applications no negative supply is required. The conditions to use a single +5V supply are: A suitable circuit for driving a plasma-type display is shown in Figure 8. The high voltage anode driver buffer is made by Dionics.
PAGE 10
ICL7135 A V+ +5 DM 8880 G RB0 PROG A RBI BI D 3K A POL G HI VOLTAGE BUFFER D1 505 +5V 5K 0V 47K The ICL7135 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated with an ICL7660 and two capacitors (Figure 12). 0.02µF 0.02µF GATES ARE 7409 0.02µF 0.02µF 2.5K Interfacing with UARTs and Microprocessors 0.02µF D1 POL D5 B8 B1 V+ DGND ICL7135 +5 0V FIGURE 8.
PAGE 11
ICL7135 41/2 DIGIT LCD DISPLAY REF VOLTAGE -5V 0.47µF 1µF 100kΩ 1µF 100kΩ INPUT 0.1µF UR 28 ICL7135 OR 27 2 REF ANALOG STROBE 26 3 COMMON R/H 25 4 INT OUT 27Ω ANALOG GND 100kΩ 28 SEGMENTS D1-D4 +5V 1 V- +5V 1 16 15 1412 5 3 4 CD4054A 7 8 13 1110 9 2 6 DIG.
PAGE 12
ICL7135 EPE TRO 1 2 3 4 5 D2 4 5 6 7 D1 B1 B2 B4 7 8 TBRL 1Y 2Y 3Y 8 74C157 1A 2A 3A D5 STROBE D5 ICL7135 ICL7135 RUN/HOLD POL 1B 2B 3B B8 D4 D3 D2 D1 B1 B2 B4 B8 NC ENABLE OVER D3 3 6 UNDER D4 2 DR TBRL TBR TBR 1 DRR POL UART IM6402/3 EPE RRI IM6402/3 SELECT TRO SERIAL OUTPUT TO RECEIVING UART STROBE +5V RUN/HOLD BUSY +5V 100pF FIGURE 13.
PAGE 13
ICL7135 Design Information Summary Sheet • CLOCK INPUT • DISPLAY COUNT The ICL7135 does not have an internal oscillator. It requires an external clock. fCLOCK (Typ) = 120kHz • CLOCK PERIOD V IN COUNT = 10, 000 × ----------------V REF • CONVERSION CYCLE tCYC = tCL0CK x 40002 when fCLOCK = 120kHz, tCYC = 333ms tCLOCK = 1 / fCLOCK • INTEGRATION PERIOD • COMMON MODE INPUT VOLTAGE tINT = 10,000 x tCLOCK (V- + 1V) < VlN < (V+ - 0.
PAGE 14
ICL7135 Die Characteristics DIE DIMENSIONS: PASSIVATION: (120 mils x 130 mils) x 525µm ±25µm Type: Nitride/Silox Sandwich Thickness: 8k Nitride over 7k Silox METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ Metallization Mask Layout ICL7135 V+ IN HI IN LO REF CAP+ REF CAP+ BUFF OUT AZ IN INT OUT ANALOG COMMON REFERENCE (MSD) D5 V- (LSB) B1 UNDERRANGE B2 OVERRANGE B4 (MSB) B8 D4 D3 STROBE D2 14 (LSD)D1 BUSY CLOCK IN POL DIGITAL GND R/H FN3093.
PAGE 15
ICL7135 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-011-AB ISSUE B) N 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -BD A2 SEATING PLANE e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.380 1.565 D1 0.005 - 0.
PAGE 16
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