Datasheet

6
FN3284.10
June 15, 2006
Application Information
Dual Slope Integrators
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor C
1
or C
2
. Another one selects e
IN
or discharges the capacitor in
preparation for the next integration cycle.
Peak Detector
A
3
acting as a comparator provides the logic drive for
operating SW
1
. The output of A
2
is fed back to A
3
and
compared to the analog input e
IN
. If e
IN
> e
OUT
the output of
A
3
is high keeping SW
1
closed. This allows C
1
to charge up
to the analog input voltage. When e
IN
goes below e
OUT
, A
3
goes negative, turning SW
1
off. The system will therefore
store the most positive analog input experienced.
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCES TEST CIRCUIT
Test Circuits and Waveforms (Continued)
0V, 2.4V
ANALYZER
+15V
V+
C
V
S1
SIGNAL
GENERATOR
R
L
GND
IN
1
V
D1
IN
2
50Ω
0V, 2.4V
NC
V-
-15V
C
V
D2
+5V
V
L
C
V
S2
+15V
V+
C
GND
V
S
V
D
IN
X
V-
-15V
C
IMPEDANCE
ANALYZER
0V, 2.4V
+5V
V
L
C
AS REQUIRED
V-
GND
-15V
IN
2
IN
1
S
3
S
1
S
2
S
4
D
1
D
2
D
3
D
4
+15V+5V
V
L
V+
DG403
C
1
C
2
e
OUT
e
IN
INTEGRATE/
SCOPE
TTL
RESET
SELECT
FIGURE 8. DUAL SLOPE INTEGRATOR
e
OUT
e
IN
C
1
R
1
SW
2
SW
1
RESET
+
-
+
-
+
-
DG401
A
1
A
3
FIGURE 9. POSITIVE PEAK DETECTOR
A
2