Datasheet

5
FN3284.10
June 15, 2006
FIGURE 2A. MEASUREMENT POINTS
C
L
includes fixture and stray capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT
FIGURE 3. CHARGE INJECTION
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. INSERTION LOSS TEST CIRCUIT
Test Circuits and Waveforms (Continued)
90%
3V
0V
t
D
0V
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
V
S1
V
S2
90%
t
D
0V
(V
O1
)
(V
O2
)
LOGIC
INPUT
V
S1
= 10V
IN
1
V+
D
1
R
L1
C
L1
V
O1
GND
V-
V
L
0V -15V
5V +15V
R
L
= 300Ω
C
L
= 35pF
D
2
R
L2
C
L2
V
O2
V
S2
= 10V
V
O
∆V
O
IN
X
ON
OFF
ON
Q = ∆V
O
x C
L
SWITCH
OUTPUT
V+
D
1
C
L
V
O
V-
R
G
V
G
V
L
0V -15V
5V +15V
GND
ANALYZER
R
L
+15V
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
V
S
V
D
IN
X
GND
+5V
V
L
C
ANALYZER
R
L
+15V
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
V
S
V
D
IN
X
GND
+5V
V
L
C