Datasheet

Chapter 2 — Theory of Operation
16 PB42 Portable Receipt Printer Service Manual
Digital to Analog Converter Signals
Maximum SPI clock frequency is 20 MHz. SPMODE[CI] = 1,
SPMODE[CP] = 0, SPMODE[REV] = 1, and SPMODE[LEN] = 0xf (16
bit transfers).
The data format is given below:
X: Do not care
SPD: Speed control bit. 1 -> fast mode 0 -> slow mode
PWR: Power control bit. 1 -> power down 0 -> normal operation
The SPD bit should always be set. (fast mode) The PWR bit should be
cleared (normal operation) when sending data, but after the end of an
audible alert, it should be set. (power down) The DAC value is sent MSB
first.
Analog to Digital Converter
The analog to digital converter (ADC) has 8 input channels (CH0 to CH7)
and produces 8-bit data. The input range is 0 to3.3V, corresponding to
output codes from 0x00 to 0xff.
The CS* line is connected to PB27. The maximum SPI clock frequency is
600 kHz. SPMODE bits CI, CP, and REV are, respectively, 0, 0, and 1.
Data transfers are 14 bits long. So, SPMODE[LEN] = 0xd.
To initiate a conversion, the chip must be enabled and a channel selected.
The first 5 bits sent to the ADC accomplish this. The first 2 bits must
always be 1’s. The following chart shows how the next 3 bits select the
channel.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X SPD PWR X New DAC value (8 bits) 0 0 0 0