Datasheet

Chapter 2 — Theory of Operation
10 PB42 Portable Receipt Printer Service Manual
• WP = 0 (Read and write allowed)
• MS = 11 (UPMB selected)
• V = 1 (Valid bank)
OR1 = 0xFF000A00:
• AM = 0xFF00 (Corresponds to 16MBytes)
• ATM = 000 (No address type mask)
• SAM = 1 (Address multiplexing enabled)
• G5LA = 0 (Output GPL5* on GPL_B5*)
• G5LS = 1 (GPL5* high on memory accesses.)
• BIH = 0 (Bursting is supported)
MAMR = 0x20904331:
• PTA = 32 (Periodic timer period = 15.625us. Assumes 66MHz clock,
SCCR[DFBRG] = 00, MPTPR[PTP] = 0x02)
• PTAE = 1 (Periodic timer enabled)
• AMA = 001 (Address multiplexing size.)
• DSA = 00 (1-cycle disable timer)
• G0CLA = 010 (A10 routed to GPL0*)
• GPLA4DIS = 0 (GPL4* is an output)
• RLFA = 0011 (Burst length is 8)
• WLFA = 0011 (Burst length is 8)
• TLFA = 0011 (1 time execution for each periodic loop)
The memory periodic timer prescaler is set to divide by 32: MPTPR =
0x0200. The UPM RAM array for 75 MHz operation should be programmed
with the following values:
• Read single beat cycle: Addresses 0x00 – 0x04 = 0x0F07FC04,
0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0X1FFFFC05
• Read burst cycle: Addresses 0x08 – 0x0F = 0x0F07FC04, 0x0FFFFC04,
0x00BDFC04, 0x00FFFC80, 0x00FFFC80, 0x00FFFC00,
0x0FF77C00, 0x1FFFFC05
• Write single beat cycle: Addresses 0x18 – 0x1D = 0x0F07FC04,
0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
0x1FFFFC05
• Write burst cycle: Addresses 0x20 – 0x28 = 0x0F07FC04,
0x0FFFFC00, 0x00BD7C00, 0x00FFFC80, 0x00FFFC80,
0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05
• Auto refresh cycle: Addresses 0x30 – 0x39 = 0x0FF77C34,
0x0FFFFC34, 0x0FF5FC34, 0x0FFFFC34, 0x0FFFFC34,