Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

Intel

Xeon™ Processor and Intel

E7500/E7501 Chipset Compatible Platform Design Guide 157

I/O Controller Hub 3 (Intel

ICH3-S)

Probing VBIAS requires the same technique as probing the RTCX1 and RTCX2 signals (using

Op-Amp). See application note AP-728, Intel

ICH Family Real Time Clock (RTC) Accuracy and

Considerations Under Test Conditions, for further details on measuring techniques.

Note: VBIAS is also very sensitive to environmental conditions.

9.6.7 SUSCLK

SUSCLK is a square waveform signal output from the RTC oscillation circuit. Depending on the

quality of the oscillation signal on RTCX1 (largest voltage swing), SUSCLK duty cycle can be

between 30% and 70%.

If the SUSCLK duty cycle is beyond the 30%–70% range, there is a poor oscillation signal on

RTCX1 and RTCX2.

SUSCLK can be probed directly using a normal probe (50

Ω input impedance probe), and it is an

appropriate signal to check the RTC frequency to determine the accuracy of the ICH3-S RTC

clock.

9.6.8 RTC-Well Input Strap Requirements

All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER#) must be either pulled up to VCCRTC

or pulled down to ground while in the G3 state. RTCRST#, when configured as shown in

Figure 9-11, meets this requirement. RSMRST# should have a weak external pull-down to ground,

and INTRUDER# should have a weak external pull-up to VCCRTC. This will prevent these nodes

from floating in G3, and correspondingly will prevent ICCRTC leakage that can cause excessive

coin-cell drain. The PWROK input signal should also be configured with an external weak

pull-down.