Intel Xeon Processor and Intel E7500/E7501Chipset Compatible Platform Design Guide

14 Intel
®
Xeon™ Processor and Intel
®
E7500/E7501 Chipset Compatible Platform Design Guide
8-14 SMBus Address Configuration .......................................................................... 122
8-15 Hot-Plug Mode .................................................................................................. 127
8-16 Frequency Matrix .............................................................................................. 128
8-17 Single-Slot Parallel Mode Hot-Plug Signal Table.............................................. 129
8-18 Hot-Plug Controller Output Signal Reset Values .............................................. 130
8-19 Dual-Slot Parallel Mode Hot-Plug Signals Table............................................... 133
8-20 Shift Register Input Data ................................................................................... 137
9-1 Bus Capacitance Reference Chart.................................................................... 152
9-2 Bus Capacitance/Pull-Up Resistor Relationship ............................................... 152
9-3 LAN Design Guide Section Reference.............................................................. 158
9-4 LCI Routing Parameter Summary ..................................................................... 160
11-1 Power Summary................................................................................................ 175
11-2 Component Recommendation—Inductor.......................................................... 188
11-3 Component Recommendation—Capacitor ....................................................... 188
11-4 Processor High-Frequency Capacitance Recommendations Per
Processor .......................................................................................................... 191
11-5 Processor Bulk Capacitance Recommendation Per Processor ........................ 192
11-6 Various Component Models Used at Intel (Not Vendor Specifications) ............ 194
11-7 Intel
®
ICH3-S Power Rail Terminology ............................................................. 201
11-8 Intel
®
ICH3-S Decoupling Recommendations................................................... 202
11-9 Intel
®
P64H2 Max Sustained Currents............................................................. 203
11-10 Decoupling Capacitor Recommendations ......................................................... 203
13-1 Processor Schematic Checklist......................................................................... 225
13-2 MCH Schematic Checklist................................................................................. 229
13-3 Intel
®
ICH3-S Schematic Checklist ................................................................... 232
13-4 Intel
®
P64H2 Schematic Checklist .................................................................... 238
13-5 CK408 Schematic Checklist.............................................................................. 242
13-6 SSI Schematic Checklist ................................................................................... 243
14-1 Processor Layout Checklist............................................................................... 245
14-2 Processor Power Delivery Layout Checklist ..................................................... 247
14-3 MCH Layout Checklist....................................................................................... 251
14-4 Intel
®
ICH3-S Layout Checklist ........................................................................ 254
14-5 Intel
®
P64H2 Layout Checklist .......................................................................... 258
14-6 SSI Layout Checklist ......................................................................................... 258